CN101228569B - Method and system for driving a light emitting device display - Google Patents

Abstract

The invention provides a method and system for driving a light emitting device display. The system provides a timing schedule that increases the accuracy of the display. The system may provide a timing schedule by which duty cycles may be consecutively implemented in a group of rows. The system may provide a timing schedule by which the aging factor is used for a plurality of frames.

Description

Method and system for driving a light emitting device display

technical field

The present invention relates to display technology, in particular to methods and systems for driving light emitting device displays. the

Background technique

Active-matrix organic light-emitting diodes (AMOLEDs) using amorphous silicon (a-Si), polysilicon, organic, or other drive backplanes have recently been developed due to their advantages over active liquid crystal displays. become more attractive. AMOLED displays utilizing a-Si backplanes have, for example, advantages including low temperature fabrication that expands the utilization of different substrates and enables flexible displays, reducing manufacturing costs. In addition, OLEDs produce high-resolution displays with wide viewing angles. the

An AMOLED display includes an array of rows and columns of pixels, each with organic light emitting diodes (OLEDs) and backplane electronics arranged in the row and column array. Because OLED is a current-driven device, the pixel circuit of AMOLED should be able to provide accurate and constant driving current. the

Figure 1 illustrates the traditional duty cycle of a conventional voltage-programmable AMOLED display. In FIG. 1, "row i (i=1, 2, 3)" means the ith row of the matrix pixel array of the AMOLED display. In FIG. 1, "C" denotes a compensation voltage generation period in which a compensation voltage is generated across the gate-source terminals of the drive transistor of the pixel circuit, "VT-GEN" denotes a _VT generation period, The threshold voltage V _T of the drive transistor is generated during the V _T generation period, "P" indicates the current stabilization period, and the pixel current is adjusted by applying a programmed voltage to the gate of the drive transistor during the current stabilization period, "D" indicates A driving period in which the OLED of the pixel circuit is driven by a current controlled by the driving transistor.

For each row of the AMOLED display, the working period includes a compensation voltage generation period "C", a _VT generation period "VT-GEN", a current stabilization period "P" and a driving period "D". In general, as shown in Figure 1, these duty cycles are performed consecutively for a matrix structure. For example, the entire programming cycle (ie, "C", "VT-GEN" and "P") is executed for the first row (ie, row 1), and then executed for the second row (ie, row 2).

However, this timing schedule cannot be used for large area displays because the V _T generation period "VT-GEN" requires a large time budget to generate accurate threshold voltages for driving TFTs. Furthermore, performing two additional duty cycles (ie, "C" and "VT-GEN") results in high power consumption and also requires additional control signals resulting in higher implementation costs.

Contents of the invention

It is an object of the present invention to provide a method and system which obviates or alleviates at least one disadvantage of existing systems. the

According to one aspect of the present invention, a display system is provided, which includes: a pixel array having a plurality of pixel circuits arranged in rows and columns. The pixel circuit has a light emitting device, a capacitor, a switching transistor, and a driving transistor for driving the light emitting device. The pixel circuit includes a path for programming the threshold of the drive transistor, and a second path for generating the threshold of the drive transistor. The system includes: a first driver for providing programming data to the pixel array; and a second driver for controlling the generation of threshold values for the drive transistors for one or more drive transistors. The first driver and the second driver drive the pixel array to independently implement programming and generating operations. the

According to another aspect of the present invention, a method for driving a display system is provided. The display system includes: a pixel array with a plurality of pixel circuits arranged in rows and columns. The pixel circuit has a light emitting device, a capacitor, a switching transistor, and a driving transistor for driving the light emitting device. The pixel circuit includes a path for programming the threshold of the drive transistor, and a second path for generating the threshold of the drive transistor. The method comprises the steps of controlling the generation of threshold values for the drive transistors for one or more drive transistors, providing programming data to the pixel array independently of the controlling step. the

According to still another aspect of the present invention, a display system is provided, which includes: a pixel array including a plurality of pixel circuits arranged in rows and columns, the pixel circuit has a light emitting device, a capacitor, a switching transistor, and a driver for driving the light emitting device transistor. The system includes: a first driver, used to provide program control data to the pixel array; and a second driver, used to generate the aging coefficient of each pixel circuit and store it in the corresponding pixel circuit , and program and drive pixel circuits in rows for a plurality of frames according to the stored aging coefficients. The pixel array is divided into segments. At least one signal line driven by the second driver for generating the aging coefficient is shared by the segments. the

According to yet another aspect of the present invention, a method for driving a display system is provided. The display system includes: a pixel array with a plurality of pixel circuits arranged in rows and columns. The pixel circuit has a light emitting device, a capacitor, a switching transistor, and a driving transistor for driving the light emitting device. The pixel array is divided into segments. The method includes the steps of: generating an aging coefficient of each pixel circuit by using segmented signals and storing the aging coefficients in corresponding pixel circuits of each row, the segmented signals being shared by each segment; and according to the stored aging The coefficients program and drive pixel circuits in rows of multiple frames. the

This summary does not necessarily describe all features of the invention. the

Description of drawings

These and other features of the present invention will become more apparent from the following description with reference to the accompanying drawings, wherein:

Figure 1 illustrates the traditional duty cycle of a conventional AMOLED display;

Figure 2 illustrates an example of a parallel dimension sequence table for a stably operating light-emitting display according to one embodiment of the present invention;

Figure 3 illustrates an example of a parallel timing table for a stably operating light-emitting display according to one embodiment of the present invention;

Figure 4 illustrates an example of an AMOLED display array structure for the timing tables of Figures 2 and 3;

FIG. 5 illustrates an example of a voltage-programmable pixel circuit, where a segmented timing table and a parallel timing table are applicable to the voltage-programmed pixel circuit. the

Figure 6 illustrates an example of a timing table applied to the pixel circuit of Figure 5;

FIG. 7 illustrates another example of a voltage-programmable pixel circuit to which a segmented timing table and a parallel timing table are applicable;

Figure 8 illustrates an example of a timing table applied to the pixel circuit of Figure 7;

Figure 9 illustrates an example of a shared signaling addressing scheme (shared signaling addressing scheme) for a light-emitting display according to one embodiment of the present invention;

Figure 10 illustrates an example of a pixel circuit where a shared signaling addressing scheme is suitable for the pixel circuit;

Figure 11 illustrates an example of a timing table applied to the pixel circuit of Figure 10;

Figure 12 illustrates the pixel current stability of the pixel circuit of Figure 10;

Figure 13 illustrates another example of a pixel circuit to which a shared signaling addressing scheme is applicable;

Figure 14 illustrates an example of a timing table applied to the pixel circuit of Figure 13;

Figure 15 illustrates an example of an AMOLED display array structure for the pixel circuit of Figure 10;

Figure 16 illustrates an example of an AMOLED display array structure for the pixel circuit of Figure 13;

Figure 17 illustrates yet another example of a pixel circuit to which a shared signaling addressing scheme is applicable;

Figure 18 illustrates an example of a timing table applied to the pixel circuit of Figure 17;

Figure 19 illustrates an example of an AMOLED display array structure for the pixel circuit of Figure 17;

Figure 20 illustrates yet another example of a pixel circuit to which a shared signaling addressing scheme is applicable;

Figure 21 illustrates an example of a timing table applied to the pixel circuit of Figure 20; and

FIG. 22 illustrates an example of an AMOLED display array structure for the pixel circuit of FIG. 20 . the

Detailed ways

This disclosure describes an embodiment that utilizes a pixel circuit having a light emitting device, such as an organic light emitting diode (OLED), and a plurality of transistors, such as thin film transistors ( thin filmtransistors, TFT) and the like, arranged in rows and columns to form an AMOLED display. The pixel circuitry may include a pixel driver for the OLED. However, a pixel may include any light emitting device other than an OLED, and a pixel may include any transistor other than a TFT. The transistors in the pixel circuit can be N-type transistors, P-type transistors or combinations thereof. The transistors in the pixels can utilize amorphous silicon, nano/microcrystalline silicon, polysilicon (poly silicon), organic semiconductor technology (such as organic TFT), NMOS/PMOS technology or CMOS technology (such as Such as MOSFET). In the specification, "pixel circuit" and "pixel" are used interchangeably. A pixel circuit may be a current-programmed pixel or a voltage-programmed pixel, and in the following description, "signal" and "row" may be used interchangeably. the

Embodiments of the present invention relate to techniques for generating precise threshold voltages for driving TFTs. As a result, a stable current can be generated despite changes in the characteristics of the pixel elements, eg due to pixel aging and process variations. It improves the brightness stability of the OLED. At the same time it also reduces power consumption and signaling, resulting in reduced implementation costs. the

Describe segmented timing tables and parallel timing tables in detail. These timing tables extend the time budget of the period used to generate the threshold voltage V _T of the drive transistor. As described below, the rows in the display array are segmented and the duty cycles are divided into categories, eg, two categories. For example, the first category includes compensation periods and V _T generation periods, while the second category includes current adjustment periods and drive periods. Duty cycles of each category are performed consecutively for each segment, while both categories are performed for two adjacent segments. For example, while the current regulation and drive cycles are performed consecutively on the first segment, the compensation and _VT generation cycles are performed on the second segment.

FIG. 2 illustrates an example of a segmented timing table for a stable operation light-emitting display according to one embodiment of the present invention. In FIG. 2, "row k" (k=1, 2, 3, . . . , j, j+1, j+2) indicates the kth row of the display array, and the arrow shows the direction of execution. the

For each row, the timing table of FIG. 2 includes a compensation voltage generation period "C", a V _T generation period "VT-GEN", a current adjustment period "D" and a driving period "P".

The timing table of Figure 2 extends the _VT generation period "VT-GEN" without affecting the programming time. To achieve this, the rows of the display array are classified into segments for which the segmented addressing scheme of FIG. 2 is applied. Each segment thus includes the row in which the _VT generation cycle is performed. In FIG. 2, row 1, row 2, row 3, . . . , and row i are in a segment of rows of the display array.

The programming of each segment begins with the execution of the first and second duty cycles "C" and "VT-GEN". Then, a current calibration period "P" is preformed for the entire segment. As a result, the time budget for the V _T generation cycle "VT-GEN" is stretched to j.τ _P , where j is the number of rows in each segment and τ _P is the time budget for the first duty cycle "C" (or current regulation cycle) time budget.

Furthermore, the frame time τ _F is Z x n x τ _P , where n is the number of rows in the display and Z is a function of the number of repetitions in the segment. For example, in Figure 2, _VT generation starts at the first row of the segment and proceeds to the last row (first repetition), then programming starts at the first row and proceeds to the last row (second repetition). Therefore, Z is set to 2. If the number of repetitions is increased, the frame time will become Z×n×τ _P , where Z is the number of repetitions and can be greater than two.

FIG. 3 illustrates an example of a parallel timing table for a stable operation light-emitting display according to one embodiment of the present invention. In FIG. 3, "row _k " (k=1, 2, 3, . . . , j, j+1) denotes the kth row of the display array.

Similar to FIG. 2, the timing table of FIG. 4 includes a compensation voltage generation period "C", a V _T generation period "VT-GEN", a current adjustment period "P" and a driving period "D" for each row.

The timing table of Figure 3 expands the time budget of the V _T generation cycle "VT-GEN", while τ _P is saved as τ _F /n, where τ _P is the time budget of the first duty cycle "C" and τ _F is the frame time , n is the number of rows in the display array. In FIG. 3, row ₁ to row _i are in segments of rows of the display array.

According to the above addressing scheme, the current regulation period "P" of each segment is preformed in parallel to the first duty cycle "C" of the next segment. Therefore, display arrays are designed to support parallel operation, that is, the ability to perform different cycles independently without affecting each other, such as compensation and generation of programmed _VT and current adjustments.

FIG. 4 illustrates an example of an AMOLED display array structure for the timing tables of FIGS. 2 and 3 . In Fig. 4, SEL[a] (a=1,...,m) represents a selection signal for selecting a row, and CTRL[b] (b=1,...,m) represents a selection signal for a row A control signal for driving a threshold voltage of a TFT is generated at each pixel, and VDATA[c] (c=1, . . . , n) represents a data signal for providing programming data. The AMOLED display 10 of FIG. 4 includes a plurality of pixel circuits 12 arranged in rows and columns, an address driver 14 for controlling SEL[a] and CTRL[b], and a data driver 16 for controlling VDATA[c]. The rows of pixel circuits 12 (eg, row ₁ , . . . , row _mh and row _m−h+1 , . . . , row _m ) are segmented as described above. In order to achieve some cycles in parallel, AMOLED display 10 is designed to support parallel operation.

FIG. 5 illustrates an example of a pixel circuit to which a segmented timing table and a parallel timing table are applicable. Pixel circuit 50 of FIG. 5 includes OLED 52 , storage capacitor 54 , driving TFT 56 and switching TFTs 58 and 60 . The selection line SEL1 is connected to the gate terminal of the switch TFT58. The selection line SEL2 is connected to the gate terminal of the switching TFT60. The first terminal of the switching TFT58 is connected to the data line VDATA, and the second terminal of the switching TFT58 is connected to the gate terminal of the driving TFT56 at the node A1. The first terminal of the switch TFT60 is connected to the node A1, and the second terminal of the switch TFT60 is connected to the ground line. The first terminal of the driving TFT 56 is connected to the controllable power supply voltage VDD, and the second terminal of the driving TFT 56 is connected to the anode of the OLED 52 at node B1. A first terminal of the storage capacitor 54 is connected to the node A1, and a second terminal of the storage capacitor 54 is connected to the node B1. Pixel circuit 50 may be utilized with segmented timing tables, parallel timing tables, and combinations thereof.

_VT is generated through transistors 56 and 60, while current regulation is performed by transistor 58 through the VDATA line. Therefore, the pixel is capable of parallel operation.

FIG. 6 illustrates an example of a timing table applied to the pixel circuit 50 . In FIG. 6, "X11", "X12", "X13", and "X14" represent duty cycles. X11 corresponds to "C" in Figures 2 and 3, X12 corresponds to "VT-GEN" in Figures 2 and 3, X13 corresponds to "P" in Figures 2 and 3, and X14 corresponds to "D" in Figures 2 and 3. the

5 and 6, the storage capacitor 54 is charged to a negative voltage (-Vcomp) during the first duty cycle X11 while the gate voltage of the driving TFT 56 is zero. During the second duty cycle X12 , node B1 is charged to −V _T , where V _T is the threshold of driving TFT 56 . Because it is pre-performed through switching transistor 60 rather than through switching transistor 58, this cycle X12 can be performed without affecting data line VDATA, so that other duty cycles can be performed for other rows. During the third duty cycle X13, the node A1 is charged to the programming voltage V _P , resulting in V _GS =V _P +V _T , where V _GS represents the gate-source voltage of the driving TFT 56 .

FIG. 7 illustrates another example of a pixel circuit to which a segmented timing table and a parallel timing table are applied. The pixel circuit 70 of FIG. 7 includes an OLED 72 , storage capacitors 74 and 76 , a driving TFT 78 and switching TFTs 80 , 82 and 84 . The first selection line SEL1 is connected to the gate terminals of the switching TFTs 80 and 82 . The second selection line SEL2 is connected to the gate terminal of the switching TFT 84. A first terminal of the switching TFT 80 is connected to the cathode of the OLED 72, and a second terminal of the switching TFT 80 is connected to the gate terminal of the driving TFT 78 at node A2. The first terminal of the switch TFT 82 is connected to the node B2, and the second terminal of the switch TFT 82 is connected to the ground line. The first terminal of the switch TFT 84 is connected to the data line VDATA, and the second terminal of the switch TFT 84 is connected to the node B2. A first terminal of the storage capacitor 74 is connected to the node A2, and a second terminal of the storage capacitor 74 is connected to the node B2. The first terminal of the storage capacitor 76 is connected to the node B2, and the second terminal of the storage capacitor 76 is connected to the ground line. The first terminal of the driving TFT 78 is connected to the cathode of the OLED 72, and the second terminal of the driving TFT 78 is connected to the ground line. The anode of the OLED 72 is connected to the controllable power supply voltage VDD. Pixel circuit 70 has the capability of employing segmented timing tables, parallel timing tables, and combinations thereof. the

_VT is generated through transistors 78, 80 and 82, while current regulation is performed by transistor 84 through the VDATA line. Therefore, the pixel is capable of parallel operation.

FIG. 8 illustrates an example of a timing table applied to the pixel circuit 70 . In FIG. 8, "X21", "X22", "X23", and "X24" represent duty cycles. X21 corresponds to "C" in Figures 2 and 3, X22 corresponds to "VT-GEN" in Figures 2 and 3, X23 corresponds to "P" in Figures 2 and 3, and X24 corresponds to "D" in Figures 2 and 3. the

Referring to FIGS. 7 and 8 , pixel circuit 70 employs a bootstrapping effect to increase the programming voltage to the stored V _T , where V _T is the threshold voltage driving TFT 78 . During the first duty cycle x21 , node A2 is charged with a compensation voltage VDD-V _OLED , where V _OLED is the voltage of OLED 72 , and node B2 is discharged to ground. During the second duty cycle X22 , the voltage at the node A2 is charged to V _T of the driving TFT 78 . Current regulation occurs in a third duty cycle X23 during which node B2 is charged to the programmed voltage _VP so that node A2 is charged to V _P +V _T .

The segmented timing table and the parallel timing table as described above provide sufficient time for the pixel circuit to generate an accurate threshold voltage for driving the TFT. As a result, a stable current is generated despite pixel aging, process variations, or a combination thereof. The duty cycle is shared by the segments so that the programming cycle of one row in the segment overlaps with the programming cycle of another row in the segment. Therefore, they can maintain a high display speed regardless of the size of the display. the

Describe the shared signaling addressing scheme in detail. The rows in the display array are divided into several segments according to a shared signaling addressing scheme. The aging coefficient of the pixel circuit (eg threshold voltage of the driving TFT, OLED voltage) is stored in the pixel. The stored aging coefficients are used for multiple frames. One or more signals required to generate the aging coefficients are shared in a segment. the

For example, the threshold voltage V _T for driving TFTs is generated simultaneously for each segment. The segment is then subjected to normal operation. All additional signals required to generate threshold voltages (eg, VSS of FIG. 10 ) other than the data and select lines are common to the rows in each segment. Utilizing a reasonable storage capacitor to store _VT results in infrequent compensation cycles because the bleed current of the TFT is small. As a result, energy consumption is drastically reduced.

Because the _VT generation cycle is performed segment by segment, the time allotted to the _VT generation cycle is expanded by the number of rows in a segment to generate a more accurate compensation. Since the bleed current of Si:TFT is small (eg, about 10 ⁻¹⁴ ), the generated V _T can be stored in a capacitor and used for several other frames. As a result, the duty cycle during the next post compensation frame is reduced to a programming and driving cycle. Therefore, the power consumption related to the external driver and related to charging/discharging parasitic capacitance is divided among the same several frames.

Figure 9 illustrates an example of a shared signaling addressing scheme for light-emitting displays according to one embodiment of the present invention. A shared signaling addressing scheme reduces interface and driver complexity. the

The display array to which the shared signaling addressing scheme is applied is divided into several segments, similar to those of FIGS. 2 and 3 . In Figure 9, "row[i, k]" (k=1, 2, 3, ..., h) indicates the k-th row in the j-th segment, and "h" is the The number of lines, "L" is the number of frames using the same generated _VT . In Fig. 9, "row [i, k]" (k=1, 2, 3, ..., h) is in one segment, "row [i-1, k]" (k=1, 2 , 3, ..., h) are in another segment.

The timing table in FIG. 9 includes a compensation period "C&VT-GEN" (for example, 301 in FIG. 9 ), a programming period "P" and a driving period "D". In addition to the normal operation of the display and the L-1 post-compensation frame period 304 as a normal operation frame, the compensation interval 300 also includes a frame generation period 302, and a compensation period "C&VT-GEN" (for example, 301 of FIG. 9 ), in which Threshold voltages for driving TFTs are generated and stored inside the pixels during the frame generation period 302 . The frame generation period 302 includes a programming period "P" and a driving period "D". The L-1 post compensation frame period 304 includes a set of consecutive programming periods "P" and driving periods "D". the

As shown in Figure 9, the drive cycle for each row starts with a delay of _τP from the previous row, where _τP is the time budget allocated to the programmed cycle "P". The time of the drive cycle "D" of the last frame is reduced by i*τ _P for each row, where "i" is the number of rows preceding that row in the segment (e.g., for [j,h] is (h-1)).

Since τ _P (eg, about 10 μs) is much smaller than the frame time (eg, about 16 ms), the effect of latency is negligible. However, to minimize this effect, the programming direction can be changed each time so that the average brightness loss due to latency becomes equal for all rows, or to account for this effect on the programming voltage of the frame before and after the compensation period. For example, the sequence of programmed rows can be changed after each _VT generation cycle (ie whether programming repeats from top to bottom or bottom to top).

Figure 10 illustrates an example of a pixel circuit for which a shared signaling addressing scheme is applicable. A pixel circuit 90 of FIG. 10 includes an OLED 92 , storage capacitors 94 and 96 , a driving TFT 98 , and switching TFTs 100 , 102 and 104 . Pixel circuit 90 is similar to pixel circuit 70 of FIG. 7 . The driving TFT 98, the switching TFT 100 and the first storage capacitor 94 are connected at node A3 catch. The switching TFTs 102 and 104 and the first and second storage capacitors 94 and 96 are connected at a node B3. OLED92, drive TFT98, and switch TFT100 are connected at node C3. The switching TFT 102, the second storage capacitor 96 and the driving TFT 98 are connected to the controllable power supply voltage VSS. the

FIG. 11 illustrates an example of a timing table applied to the pixel circuit 90 . In FIG. 11, "X31", "X32", "X33", "X34", and "X35" represent duty cycles. X31 , X32 and X33 correspond to the compensation cycle (for example, 301 in FIG. 9 ), X34 corresponds to “P” in FIG. 9 , and X35 corresponds to “D” in FIG. 9 . the

Referring to FIGS. 10 and 11 , pixel circuit 90 employs a bootstrapping effect to increase the programming voltage to a generated V _T , where V _T is the threshold voltage driving TFT 98 . The compensation period (for example, 301 in FIG. 9 ) includes the first three periods X31, X32 and X33. During the first duty cycle X31 , the node A3 is charged to the compensation voltage VDD-V _OLED . The time of the first duty cycle X31 is small to control the influence of unwanted emissions. During the second duty cycle X32, VSS rises to a high positive voltage V1 (eg, V1=20V), so node A3 is self-booted to high voltage, and node C3 rises to V1, causing OLED 92 to be turned off. During the third duty cycle X33, the voltage of the node A3 is discharged through the switching TFT 100 and the driving TFT 98, and is reduced to V2+V _T , where V _T is the threshold voltage of the driving TFT 98, and V2 is 16V, for example. Before the current stabilization period, VSS goes to zero and node A3 goes to _VT . The programming voltage V _PG is added to the generated V _T by bootstrapping during the fourth duty cycle X34 . The current regulation occurs in the fourth working cycle X34, during which the node B3 is charged to the programmed voltage V _PG (eg, V _PG =6V). The voltage at node A3 therefore becomes V _PG +V _T , thereby generating an overload voltage independent of V _T . The current of the pixel circuit becomes independent of the V _T transition during the fifth period X35 (drive period). Here, the first storage capacitor 94 is used to store the V _T during the V _T generation interval.

FIG. 12 illustrates the pixel current stability of the pixel circuit 90 of FIG. 10 . In FIG. 12 , “ΔV _T ” represents a change in the threshold voltage of the driving TFT (for example, 98 in FIG. 10 ), and “Ipixel error (%)” represents a change in pixel current caused by ΔV _T. As shown in FIG. 12, the pixel circuit 90 of FIG. 10 provides a highly stable current even after a 2V change in _VT of the driving TFT.

Figure 13 illustrates another example of a pixel circuit to which a shared signaling addressing scheme is applied. The pixel circuit 110 of FIG. 13 is similar to the pixel circuit 90 of FIG. 10 , however, it includes two switching TFTs. Pixel circuit 110 includes OLED 112, storage capacitor 114 and 116 . Driving TFT 118 and switching TFTs 120 and 122 . The driving TFT 118, the switching TFT 120 and the first storage capacitor 114 are connected at a node A4. The switching TFT 122 and the first and second storage capacitors 114 and 116 are connected at a node B4. The cathode of OLED112, drive TFT118, and switch TFT120 are connected at node C4. The second storage capacitor 116 and the driving TFT 118 are connected to a controllable power supply voltage VSS. the

FIG. 14 illustrates an example of a timing table applied to the pixel circuit 110 . In FIG. 15, "X41", "X42", "X43", "X44", and "X45" represent duty cycles. X41 , X42 and X43 correspond to the compensation period (for example, 301 in FIG. 9 ), X44 corresponds to “P” in FIG. 9 , and X45 corresponds to “D” in FIG. 9 . the

Referring to Figures 13 and 14, the pixel circuit 110 uses self-booting to add a programming voltage to the generated _VT . The compensation period (for example, 301 in FIG. 9 ) includes the first three periods X41, X42 and X43. During the first duty cycle X41, the node A4 is charged to the compensation voltage VDD-V _OLED . The time of the first duty cycle X41 is small to control the influence of unwanted emissions. During the second duty cycle X42, VSS rises to a high positive voltage V1 (eg, V1=20V), so node A4 is self-booted to high voltage, and node C4 also rises to V1, causing OLED 112 to be turned off. During the third duty cycle X43, the voltage of the node A4 is discharged through the switching TFT 120 and the driving TFT 118, and is reduced to V2+V _T , where V _T is the threshold voltage of the driving TFT 118, and V2 is 16V, for example. Before the current stabilization period, VSS goes to zero and node A4 goes to _VT . The programming voltage V _PG is added to the generated V _T by bootstrapping during the fourth duty cycle X44 . The current regulation occurs in the fourth working cycle X44, during which the node B4 is charged to the programmed voltage V _PG (eg, V _PG =6V). The voltage at node A4 therefore becomes V _PG +V _T , thereby generating an overload voltage independent of V _T . The current of the pixel circuit becomes independent of the V _T transformation during the fifth period X45 (drive period). Here, the first storage capacitor 114 is used to store the V _T during the V _T generation interval.

FIG. 15 illustrates an example of an AMOLED display structure for the pixel circuit of FIG. 10 . In Figure 15, GSEL[a] (a=1,...,k) corresponds to SEL2 in Figure 10, SEL1[b] (b=1,...,m) corresponds to SEL1 in Figure 10, GVSS [c] (c=1, . . . , k) corresponds to VSS in FIG. 10 , and VDATA[d] (d=1, . . . , n) corresponds to VDATA in FIG. 10 . The AMOLED display 200 of FIG. 15 includes a plurality of pixel circuits 90 arranged in rows and columns, an address driver 204 for controlling GSEL[a], SEL1[b] and GVSS[c], and an address driver 204 for controlling VDATA[s] data driver 206. The rows of pixel circuits 90 are segmented as described above. In Figure 15, segment [1] and segment [k]. the

Referring to Figures 10 and 15, the SEL2 and VSS signals of the rows in one segment communicate with each other and form the GSEL and GVSS signals. the

Figure 16 illustrates an example of an AMOLED display structure for the pixel circuit of Figure 14. In Figure 17, GSEL[a] (a=1,...,k) corresponds to SEL2 in Figure 14, SEL1[b] (b=1,...,m) corresponds to SEL1 in Figure 14, GVSS[c] (c=1, . . . , k) corresponds to VSS in FIG. 14 , and VDATA[d] (d=1, . . . , n) corresponds to VDATA in FIG. 14 . The AMOLED display 210 of FIG. 16 includes a plurality of pixel circuits 110 arranged in rows and columns, an address driver 214 for controlling GSEL[a], SEL1[b] and GVSS[c], and an address driver 214 for controlling VDATA[s ] data driver 216. The rows of pixel circuits 110 are segmented as described above. In FIG. 15, segment [1] and segment [k] are shown as examples. the

Referring to Figures 14 and 16, the SEL2 and VSS signals of a row in a segment communicate with each other and form the GSEL and GVSS signals. the

Referring to Figures 15 and 16, a display array can reduce its area by sharing the VSS and GSEL signals between physically adjacent rows. Furthermore, GVSS and GSEL in the same segment are merged and form segmented GVSS and GSEL lines. Therefore, the control signal is reduced. In addition, the number of blocks of driving signals is also reduced, resulting in reduced power consumption and reduced implementation costs. the

Figure 17 illustrates another example of a pixel circuit to which a shared signaling addressing scheme is applied. The pixel circuit of FIG. 17 includes an OLED 132 , storage capacitors 134 and 136 , a driving TFT 138 , and switching TFTs 140 , 142 and 144 . The first selection line SEL is connected to the gate terminal of the switching TFT 142 . The second selection line GSEL is connected to the gate terminal of the switching TFT 144 . The GCOMP signal line is connected to the gate terminal of the switching TFT 140 . The first terminal of the switch TFT 140 is connected to the node A5, and the second terminal of the switch TFT 140 is connected to the node C5. The first terminal of the driving TFT 138 is connected to the node C5 , and the second terminal of the driving TFT 138 is connected to the anode of the OLED 132 . The first terminal of the switch TFT 142 is connected to the data line VDATA, and the second terminal of the switch TFT 142 is connected to the node B5. The first terminal of the switch TFT 144 is connected to the power supply voltage VDD, and the second terminal of the switch TFT 144 is connected to the node C5. A first terminal of the first storage capacitor 134 is connected to the node A5, and a second terminal of the first storage capacitor 134 is connected to the node B5. The first terminal of the second storage capacitor 136 is connected to the node B5, and the second terminal of the second storage capacitor 136 is connected to VDD catch. the

FIG. 18 illustrates an example of a timing table applied to the pixel circuit 130 . In FIG. 18 , duty cycles X51 , X52 , X53 and X54 form a frame generation cycle (eg, 302 in FIG. 9 ), and the second duty cycles X53 and X54 form a post-compensation frame cycle (eg, 304 in FIG. 9 ). X53 and X54 are normal duty cycles, while the rest are compensation cycles. the

Referring to FIGS. 17 and 18 , the pixel circuit 130 uses a self-bootstrap action to add a programming voltage to the generated V _T , where V _T is the threshold voltage of the drive TFT 138 . The compensation cycle (eg 301 in FIG. 9 ) includes two cycles X51 and X52 at first. During the first working cycle X51, the node A5 is charged to the compensation voltage, and the node B5 is charged to V _REF through the switch TFT 142 and VDATA. The time of the first duty cycle X51 is small to control the influence of unwanted emissions. During the second duty cycle X52 GSEL goes to zero, so it turns off switching TFT 144 . The voltage at node A5 is discharged through the switching TFT 140 and the driving TFT 138 and drops to V _OLED +V _T , where V _OLED is the voltage of the OLED 132 and V _T is the threshold voltage of the driving TFT 138 . During the programming period, that is, during the third working period X53, the node B5 is charged to V _P +V _REF , where V _P is the programming voltage. Therefore, the gate voltage of the driving TFT 138 becomes V _OLED +V _T +V _P . Here, the first storage capacitor 134 is used to store V _T +V _OED during the compensation interval.

FIG. 19 illustrates an example of an AMOLED display array structure for the pixel circuit 130 of FIG. 17 . In Figure 19, GSEL[a] (a=1,...,k) corresponds to GSEL in Figure 17, SEL[b] (b=1,...,m) corresponds to SEL1 in Figure 17, GCMP [c] (c=1, . . . , k) corresponds to GCOMP in FIG. 17 , and VDATA[d] (d=1, . . . , n) corresponds to VDATA in FIG. 17 . The AMOLED display 220 of FIG. 19 includes a plurality of pixel circuits 130 arranged in rows and columns, an address driver 224 for controlling SEL[a], GSEL[b], and GCOMP[c], and an address driver 224 for controlling VDATA[c]. data driver 226 . As described above, the rows of pixel circuits 130 are segmented (eg, segment[1] and segment[k]). the

As shown in Figures 17 and 19, the GSEL and GCOMP signals in one segment are connected to each other and form GSEL and GCOMP lines. The GSEL and GCOMP signals are shared in segments. Furthermore, GVSS and GSEL in the same segment are merged and form segmented GVSS and GSEL lines. Therefore, the control signal is reduced. In addition, the number of blocks of driving signals is also reduced, resulting in reduced power consumption and reduced implementation costs. the

Figure 20 illustrates another example of a pixel circuit to which a shared addressing scheme is applied. The pixel circuit 150 of FIG. 20 is similar to the pixel circuit 130 of FIG. 17 . pixel electricity Circuit 150 includes OLED 152 , storage capacitors 154 and 156 , driving TFT 158 , and switching TFTs 160 , 162 and 164 . The gate terminal of the switching TFT 164 is connected to the controllable power supply voltage VDD instead of GSEL. The driving TFT 158, the switching TFT 162 and the first storage capacitor 154 are connected at a node A6. The switching TFT 162 and the first and second storage capacitors 154 and 156 are connected at a node B6. The driving TFT 158 and the switching TFTs 160 and 164 are connected to the node C6. the

FIG. 21 illustrates an example of a timing table applied to the pixel circuit 150 . In FIG. 21 , working cycles X61 , X62 , X63 and X64 form a frame generation cycle (such as 302 in FIG. 9 ), and the second working cycles X63 and X64 form a post-compensation frame cycle (such as 304 in FIG. 9 ). the

Referring to FIGS. 20 and 21 , the pixel circuit 150 uses self-bootstrapping to add a programming voltage to the generated V _T , where V _T is the threshold voltage for driving the TFT 158 . The compensation period (for example, 301 in FIG. 9 ) includes the first two periods X61 and X62. During the first working cycle X61, the node A6 is charged to the compensation voltage, and the node B6 is charged to V _REF through the switch TFT 162 and VDATA. The time of the first duty cycle x61 is small to control the effect of unwanted emissions. During the second duty cycle x62, VDD goes to zero, so it turns off the switching TFT 164. The voltage of the node A6 is discharged through the switching TFT 160 and the driving TFT 158 and is reduced to V _OLED +V _T , where V _OLED is the voltage of the OLED 152 and V _T is the threshold voltage of the driving TFT 158 . During the programming period, that is, during the third working period x63, the node B6 is charged to V _P +V _REF , where V _P is the programming voltage. It has been identified, so the gate voltage driving TFT 158 becomes V _OLED +V _T +V _P . Here, the first storage capacitor 154 is used to store V _T +V _OLED during the compensation interval.

FIG. 22 illustrates an example of an AMOLED display array structure for the pixel circuit 150 of FIG. 20 . In Figure 22, SEL[a] (a=1,...,m) corresponds to SEL in Figure 22, GCMP[b] (b=1,...,k) corresponds to GCOMP in Figure 22, GVDD [c] (c=1, . . . , k) corresponds to VDD in FIG. 22 , and VDATA[d] (d=1, . . . , k) corresponds to VDATA in FIG. 22 . The AMOLED display 230 of FIG. 22 includes a plurality of pixel circuits 150 arranged in rows and columns, an address driver 234 for controlling SEL[a], GCOMP[b], and GVDD[c], and an address driver 234 for controlling VDATA[c]. data driver 236 . As with the pixels described above, the rows of circuit 330 are segmented (eg, segment[1] and segment[k]). the

20 and 22, the VDD and GCOMP signals of rows in one segment are connected to each other and form the GVDD and GCOMP lines. The GVDD and GCOMP signals are shared in a segment. In addition, GVDD and GCOMP in the same segment are merged and form segmented GVDD and GCOMP line. Therefore, the control signal is reduced. In addition, the number of blocks of driving signals is also reduced, resulting in lower power consumption and lower implementation costs. the

According to an embodiment of the present invention, duty cycles are shared among segments to generate precise threshold voltages for driving TFTs. This reduces power consumption and signal consumption, resulting in lower implementation costs. The duty cycle of one row in the segment overlaps with the duty cycle of another row in the segment. Therefore, they can maintain a high display speed regardless of the size of the display. the

The accuracy of the generated _VT depends on the time allotted to the _VT generation cycle. The generated _VT is a function of the storage capacitance and driving TFT parameters, as a result, a specific mismatch affects the mismatch-related generated _VT in the storage capacitor for a given threshold voltage of the driving transistor. The increase in _VT generation cycle time reduces the effect of certain mismatches on the generated _VT . According to embodiments of the present invention, the time allotted to _VT is scalable without affecting the frame frequency or reducing the number of rows, thus reducing imperfect compensation and spatial mismatch regardless of the size of the panel Influence.

The _VT generation time is increased to achieve high precision recovery of the threshold voltage _VT of the driving TFT across its gate-source terminal. As a result, the uniformity of the panel is improved. In addition, the pixel circuitry of the addressing scheme has the ability to supply significantly higher currents as the pixel ages in order to compensate for the reduction in OLED brightness.

According to embodiments of the present invention, the addressing scheme improves backplane stability and also compensates for OLED brightness reduction. Compared with existing compensation driving schemes, the overhead of power consumption and implementation cost is reduced by more than 90%. the

Since the shared addressing scheme ensures low power consumption, it is suitable for low power applications such as mobile applications. The mobile application may be, but not limited to, personal digital assistants (Personal Digital Assistants, PDA), Internet phone, and the like. the

All cited documents are hereby incorporated by reference. the

The invention has been described with reference to one or more embodiments. However, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope of the present invention defined in the claims. the

Claims (32)

1. display system comprises:

Pel array; It comprises a plurality of image element circuits of arranging with linescan method; Each said image element circuit has luminescent device, capacitor, first switching transistor and is used for the driving transistors of driven for emitting lights device, and said image element circuit comprises the path of the threshold voltage that is used for program control said driving transistors and is used to generate the alternate path of the threshold voltage of said driving transistors;

First driver is used for to pel array programmable data being provided; And

Second driver is used to the generation of the transistorized threshold voltage of one or more driving transistors controlling and driving, and said first driver and the said pel array of said second driver drives are to realize program control and generating run independently.

2. display system according to claim 1; Wherein said image element circuit is divided into a plurality of segmentations, and said first driver and the said pel array of said second driver drives are to realize program control operation and another segmentation is realized generating run to a segmentation.

3. display system according to claim 2, wherein each segmentation comprises multirow, and the every row in the segmentation is carried out generating run continuously.

4. display system according to claim 1, wherein said image element circuit is divided into a plurality of segmentations, and each segmentation comprises multirow, and the every row in the segmentation is carried out generating run continuously.

5. display system according to claim 1, wherein said driving transistors is connected to the controllable voltage line.

6. display system according to claim 5; Wherein said first switching transistor is connected to said capacitor and the data line that is used to provide said data; The grid of said first switching transistor is connected with first selection wire, and wherein said image element circuit further comprises:

The second switch transistor, it is connected to the grid of said capacitor and said driving transistors, and the transistorized grid of said second switch is connected with second selection wire.

7. display system according to claim 5, wherein said first switching transistor are connected to said capacitor and the data line that is used to provide said data, and the grid of said first switching transistor is connected with first selection wire; And wherein said image element circuit further comprises:

The second switch transistor, it is connected to the grid of said capacitor and said driving transistors, and the transistorized grid of said second switch is connected with second selection wire; With

The 3rd switching transistor, it is connected to said capacitor and said first switching transistor, and the grid of said the 3rd switching transistor is connected with said second selection wire.

8. according to claim 6 or 7 described display systems, wherein said second driver is operated said first selection wire and said second selection wire.

9. according to claim 6 or 7 described display systems, wherein said capacitor comprises:

First capacitor, its first end is connected to the grid of said driving transistors, second end be connected to said first switching transistor and

Second capacitor, its first end is connected to second end of said first switching transistor and said first capacitor, makes said first capacitor be connected with said second capacitors in series.

10. method that is used for the driving display system; Said display system comprises pel array; Said pel array comprises a plurality of image element circuits of arranging with linescan method; Each said image element circuit has luminescent device, capacitor, switching transistor and is used for the driving transistors of driven for emitting lights device, the alternate path that said image element circuit comprises the path that is used for the transistorized threshold voltage of program control driving and is used to generate the threshold voltage of driving transistors, and said method comprises the steps:

Be the generation of the threshold voltage of the driving transistors of one or more driving transistorss control image element circuits,

Be independent of controlled step, programmable data be provided to pel array.

11. method according to claim 10, wherein said image element circuit is divided into a plurality of segmentations, and each segmentation comprises multirow, and said controlled step is carried out generating run continuously to each row in the segmentation.

12. a display system comprises:

Pel array comprises a plurality of image element circuits of arranging with linescan method, and each said image element circuit has luminescent device, capacitor, first switching transistor and is used for the driving transistors of driven for emitting lights device, and the row of image element circuit is divided into a plurality of segmentations;

First driver is used for to pel array programmable data being provided; And

Second driver is used for through operating in segmentation by shared line, generates the threshold voltage of the driving transistors of each image element circuit in the said segmentation and is stored in the corresponding image element circuit.

13. display system according to claim 12, wherein under the control of first and second drivers, the sequence of program control row is variable in the segmentation.

14. display system according to claim 13; Wherein backoff interval is assigned to each segmentation to show; Backoff interval comprises compensation cycle, and the frame that is used to generate said threshold voltage generates the cycle, and the post compensation frame period of the normal running that is used for being the basis with the said threshold voltage that generates in the frame generation cycle; The post compensation frame period has L-1 cycle, and wherein L representes the frame number in the backoff interval.

15. display system according to claim 12, wherein said first switching transistor are connected to said capacitor and the data line that is used to provide said data, the grid of said first switching transistor is connected with first selection wire; And wherein said image element circuit further comprises:

The second switch transistor, it is connected to the grid of said capacitor and said driving transistors, and the transistorized grid of said second switch is connected with second selection wire.

16. display system according to claim 12, wherein said first switching transistor are connected to said capacitor and the data line that is used to provide said data, the grid of said first switching transistor is connected with first selection wire; And wherein said image element circuit further comprises:

The second switch transistor, it is connected to the grid of said capacitor and said driving transistors, and the transistorized grid of said second switch is connected with second selection wire; With

The 3rd switching transistor, it is connected to said capacitor and said first switching transistor, and the grid of said the 3rd switching transistor is connected with said second selection wire.

17. according to claim 15 or 16 described display systems, at least one in wherein said first selection wire and said second selection wire is by shared line in said segmentation.

18. according to claim 15 or 16 described display systems, wherein said driving transistors is connected to by the shared controllable voltage line of said segmentation.

19. display system according to claim 12, wherein said image element circuit comprises:

First switching transistor, it is connected to said capacitor and the data line that is used to provide said data, and the grid of said first switching transistor is connected with first selection wire;

The second switch transistor, it is connected to the grid of said capacitor and said driving transistors, and the transistorized grid of said second switch is connected with second selection wire; With

The 3rd switching transistor, it is connected to said driving transistors and pressure-wire, and the grid of said the 3rd switching transistor is connected with the 3rd selection wire.

20. display system according to claim 19, at least one in wherein said first selection wire, second selection wire and the 3rd selection wire is shared by said segmentation.

21. display system according to claim 12, wherein said first switching transistor are connected to said capacitor and the data line that is used to provide said data, the grid of said first switching transistor is connected with first selection wire; And wherein said image element circuit further comprises:

The second switch transistor, it is connected to the grid of said capacitor and said driving transistors, and the transistorized grid of said second switch is connected with second selection wire; With

The 3rd switching transistor, it is connected to said driving transistors and pressure-wire, and the grid of said the 3rd switching transistor is connected with said pressure-wire.

22. display system according to claim 21, at least one in wherein said first selection wire and said second selection wire is by shared line in said segmentation.

23. according to each the described display system in the claim 15,16,19 and 21, wherein said capacitor comprises:

First capacitor, its first end is connected to the grid of said driving transistors, second end be connected to said first switching transistor and

Second capacitor, its first end is connected to second end of said first switching transistor and said first capacitor, makes said first capacitor be connected with said second capacitors in series.

24. method that is used for the driving display system; Said display system comprises pel array; Said pel array comprises a plurality of image element circuits of arranging with linescan method; Each said image element circuit has luminescent device, capacitor, switching transistor and is used for the driving transistors of driven for emitting lights device, and said pel array is divided into a plurality of segmentations, and said method comprises the steps:

Utilize block signal generate each image element circuit in the segmentation driving transistors threshold voltage and said threshold voltage stored in the respective pixel circuit in the said segmentation; And

Serve as basic program control and drive each image element circuit in the said segmentation with the threshold voltage of being stored.

25. method according to claim 24 also comprises the step that changes the sequence of program control row in the segmentation.

26. method according to claim 25; Wherein backoff interval is assigned to each segmentation to show; Backoff interval comprises compensation cycle, and the frame that is used to generate aging coefficient generates the cycle, and the post compensation frame period that is used for being utilized in the normal running of the aging coefficient that the frame generation cycle generates; The post compensation frame period has L-1 cycle, and wherein L representes the frame number in the backoff interval.

27. according to claim 1 or 12 described display systems, wherein at least one transistor be utilize amorphous silicon, Nano/micron crystalline silicon, polysilicon, comprise the organic semiconductor of organic transistor, the NMOS/PMOS technology that comprises MOSFET or CMOS technology, P-type material or n type material make.

28. the pixel driver of a luminescent device comprises:

Capacitor, switching transistor and driving transistors by any definition in the claim 6,7,15,16,19 and 21.

29. pixel driver according to claim 28, wherein at least one transistor be utilize amorphous silicon, Nano/micron crystalline silicon, polysilicon, comprise the organic semiconductor of organic transistor, the NMOS/PMOS technology that comprises MOSFET or CMOS technology, P-type material or n type material make.

30. method according to claim 11 comprises:

After subsequently second segmentation in said a plurality of segmentations being carried out controlled step and step is provided, subsequently first segmentation in said a plurality of segmentations is carried out controlled step and step is provided.

31. method according to claim 10 wherein when to the second row execution step being provided, is carried out controlled step to first row.

32. method according to claim 24; Wherein for each segmentation, the threshold voltage of the driving transistors of each image element circuit in said generation segmentation and the step that said threshold voltage is stored in the respective pixel circuit in the said segmentation repeat program control and actuation step afterwards.

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