CN108665916A - A kind of memory modules and its implementation of Android embedded devices - Google Patents
A kind of memory modules and its implementation of Android embedded devices Download PDFInfo
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- CN108665916A CN108665916A CN201810310030.0A CN201810310030A CN108665916A CN 108665916 A CN108665916 A CN 108665916A CN 201810310030 A CN201810310030 A CN 201810310030A CN 108665916 A CN108665916 A CN 108665916A
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- 230000015654 memory Effects 0.000 title claims abstract description 198
- 239000002245 particle Substances 0.000 claims description 14
- 238000003780 insertion Methods 0.000 claims description 5
- 230000037431 insertion Effects 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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Abstract
The invention discloses a kind of memory modules and its implementation of Android embedded devices, which includes：Multiple memory grain slots position, four groups of configuration wire jumpers and the hardware interface being connect with CPU；Wherein, the parameter for the memory grain for being inserted into memory grain in memory grain slot position, and being each inserted into is identical；According to the memory grain parameter for being inserted into memory grain slot position, four groups of configuration wire jumpers select to connect matched corresponding configuration respectively.The present invention is by Android embedded device memory modules, and the circuit configuration of former memory on board is adapted to by wire jumper, the circuit interface of the circuit interface for making memory and CPU separates, the configuration variance of control signal, the address pins that shielding memory grain is brought etc., in the case where not changing circuit, realizes the compatible replacement between Android embedded device memory different models, simplify the hardware design of complete machine, it is cost-effective, improve flexibility and production efficiency.
Description
Technical field
The present invention relates to Android embedded devices, and in particular to a kind of memory modules of Android embedded devices and
Its implementation.
Background technology
Memory modules can simply be interpreted as the standard memory slot quantity that chipset can be supported, due to every money chip
Group is different with data width degree of support for the data depth of memory chip, actually also just determines each memory BANK's
Maximum capacity, and then also just determine that the memory BANK quantity that chipset can be supported (indicates the physical memory banks of the memory
Quantity).And the actual memory particle number of slots amount of memory modules and the standard memory particle number of slots amount of memory modules may
It is different, if such as 865PE mainboards be reduced to 2 from 4, the memory that capacity is 1GB is inserted into every memory grain slot position
Particle, this maximum memory capacity that the mainboard can be caused to can be supported drops to 2GB from 4GB, if 865PE mainboard memory grains
Number of slots amount increases to 6 or more from 4, then not will increase its support maximum memory capacity, still only 4GB, because
It is to share original memory circuit arrangement with original memory grain slot position in fact for increased memory grain slot position, memory modules
BANK does not also change.
Currently, memory modules have formulated clear specification DIMM (Dual-Inline-Memory- in PC industry fields
Modules, dual inline memory module), DIMM provides 64 data channel, has 168 pins, than simm slot
Want longer, and it also supports 168 novel line EDO-DRAM memories, operating voltage to be generally 3.3V and (use EDORAM
Except 168 line memory bars of memory chip), be applied to PC (Personal Computer, personal computer) machine based on x86,
The fields such as notebook, server；And in Android embedded devices also without related general specification.
The standardized memory interface mechanism of PC is briefly described below, with the SODIMM (Small of notebook
Outline Dual In-line Memory Module, small outline dual inline memory modules) for memory interface DDR3, such as
Shown in Fig. 1, physical aspect has 204 PIN foot, length and width to distinguish 67.2mm, 31.75mm；SPD (the Serial that PC memory item has
Presence Dectect, there are serial sensings for module) chip stores various configuration parameter information (such as Bank numbers of memory
Amount, voltage, sequential, row address/column address quantity, data bit width etc.), SPD is written when being produced by memory modules manufacturer, PC's
BIOS (Basic Input Output System, basic input output system) is according to the SPD on memory modules (PC memory item)
The information of chip storage establishes the data channel of CPU and memory bar come the electrical sequential etc. that north bridge Memory Controller Hub is arranged.
And for Android embedded devices, entire PCB (Printed Circuit Board, printed circuit board) plate can
Can be less than 60mm, memory chip is typically directly welded on pcb board, occupies size in 30mm；It is utilized different from PC memory item
The information of SPD storages establishes the data channel of CPU (Central Processing Unit, central processing unit) and memory bar,
The usually direct-connected memory chip of the embedded type CPU of Android embedded devices, the parameter setting between CPU and memory chip are logical
The design of oversampling circuit element is fixed, and such as a CPU, is connected the memory chip particles of 8bit bit wides and is connect the interior of 16bit bit wides
It is different to deposit chip pellet design, if equipment is designed using 4 layers of pcb board and 2 layers of pcb board, the circuit sending and receiving of memory chip particle are again
It is entirely different.
As it can be seen that Android embedded devices are designed since main memory circuit cures, flexibility is low, can not change memory
In the case of circuit, flexibly replaced between the memory chip particle of realization different designs parameter.
Invention content
The technical problem to be solved by the present invention is to Android embedded devices to design since main memory circuit cures, flexibly
Property it is low, can not in the case where not changing main memory circuit, realize different designs parameter memory chip particle between flexibly replace
The problem of.
In order to solve the above-mentioned technical problem, the technical solution adopted in the present invention is to provide that a kind of Android is embedded to be set
Standby memory modules, including：Multiple memory grain slots position, four groups of configuration wire jumpers and the hardware interface being connect with CPU；
Wherein, the parameter phase for the memory grain for being inserted into memory grain in memory grain slot position, and being each inserted into
Together；
According to the memory grain parameter for being inserted into memory grain slot position, four groups of configuration wire jumpers select to connect respectively matched
Corresponding configuration.
In above-mentioned memory modules, four groups of configuration wire jumpers include that clock configuration wire jumper, capacity configuration wire jumper, address are matched
Set wire jumper, power configuration wire jumper.
In above-mentioned memory modules, according to the configuration parameter of multiple memory grains, four groups of configuration wire jumpers select to connect respectively
Matched corresponding configuration, specially：
Clock configures wire jumper, and being adapted to corresponding clock according to memory grain working frequency configures；
Capacity configuration wire jumper must be configured by insertion memory grain capacity to different capabilities；
Address configuration wire jumper, according to coming in and going out, memory grain difference bit wide is adapted to corresponding address configuration；
Power configuration wire jumper is adapted to corresponding power configuration according to the operating voltage for being inserted into memory grain.
In above-mentioned memory modules, the hardware interface being connect with CPU is PIN pin forms.
In above-mentioned memory modules, the PIN pins of the hardware interface being connect with CPU have 112.
In above-mentioned memory modules, the memory modules are the fixed-size veneer that PCB is formed, and 112 PIN pins exist
The obverse and reverse sides of the veneer are arranged according to odd, even sequence crossover.
In above-mentioned memory modules, the PIN pins are specifically defined as respectively：
Data line DQ [31:0]；
Data strobe DQS [3:0]；
Data strobe complementation DQS# [3:0]；
Data mask [3:0]；
Clock signal CK；
Complementary clock signals CK#；
Clock enable signal CKE [1:0]；
Bank BA[2:0]；
Address wire A [15:0]
Column address strobe CAS；
Row address strobe RAS；
Write enabled WE；
On piece terminal coupling ODT [1:0]；
Piece selects CS [1:0]；
Reset RST；
Reference voltage VREF [1:0]；
Power vd D [3:0]；
Power ground VSS [7:0]；
Matching voltage VTT；
Clock configures wire jumper J1 [3:0]；
Capacity configuration wire jumper J2 [1:0]；
Address configuration wire jumper J3 [3:0]；
Address configuration wire jumper J4 [3:0].
In above-mentioned memory modules, the memory grain number of slots amount is four, and pluggable memory grain quantity is 2n, n
Take 0,1,2.
In above-mentioned memory modules, the concrete configuration that four groups of configuration wire jumpers provide is assigned as：
Clock configures wire jumper and provides DDR3 400, DDR3 533, DDR3 667, DDR3 for the memory grain being inserted into
Tetra- kinds of working frequency configurations of 800MHz；
Capacity configuration wire jumper provides tetra- kinds of capacity configurations of 512MB, 1GB, 2GB, 4GB to Android embedded devices；
Address configuration wire jumper provides row, column address line combination 12~16 row for the memory grain being inserted into, the address of 9~12 row
Configuration；
Power configuration wire jumper provides tri- kinds of typical supply voltage 1.2,1.35,1.6V power configurations, as in insertion
Deposit the operating voltage of particle.
The present invention also provides a kind of implementation methods of the memory modules of Android embedded devices, include the following steps：
Step S10, multiple memory grain slots position, four groups of configuration wire jumpers are set；
Step S20, according to Android embedded device memory bar demands, respective numbers are inserted into memory grain slot position
Memory grain, and memory grain parameter is identical；
Step S30, according to the memory grain parameter for being inserted into memory grain slot position, four groups of configuration wire jumpers select to connect respectively and
Its matched corresponding configuration；
Four groups of configuration wire jumpers include clock configuration wire jumper, capacity configuration wire jumper, address configuration wire jumper, power configuration jump
Line.
Compared with prior art, the present invention can simplify Android embedded device memory modules, hardware manufacturer
Memory design designs hardware interface for memory modules, and designs circuit without being directed to memory chip again, such as market Samsung, magnesium
Light, Hynix provide 128MB, 256MB, 512MB capacity specifications individual particle, and producer has selected 2 512MB pellet designs 1GB
Memory size circuit, after first batch produces hardware, in the case where not changing circuit, next batch cannot replace the prior art
Change 4 256MB capacity memory grains into, and Android embedded devices memory modules provided by the invention, it is adapted to by wire jumper
The circuit interface of the circuit configuration of former memory on board, the circuit interface for making memory and CPU separates, the control that shielding memory grain is brought
The configuration variance of signal processed, address pins etc., realize between Android embedded device memory different models it is compatible replace,
It is cost-effective；Apply in equipment, produced in equipment or after sale in directly the memory modules of faulty equipment can be removed, replace,
Simple and convenient, flexibility improves, and production efficiency is greatly improved.
Description of the drawings
Fig. 1 is the positive and negative schematic diagram of the SODIMM memory interface memory modules of notebook；
Fig. 2 is a kind of structural schematic diagram of the memory modules of Android embedded devices provided by the invention；
Fig. 3 is a kind of positive and negative schematic diagram of the memory modules of Android embedded devices provided by the invention；
Fig. 4 is a kind of structural representation of the example IV of the memory modules of Android embedded devices provided by the invention
Figure.
Specific implementation mode
The present invention moves to direct-connected mechanism on independent module, realizes to Android embedded device memory standards
Module, and by the circuit configuration of the former memory on board of jumper switch adaptation, make the circuit interface of memory and the circuit interface point of CPU
It opens, shields the configuration variance for controlling signal, address pins etc. that the memory grain of different designs parameter is brought, realization pair
Compatible replacement between the memory grain different model of Android embedded devices.With reference to the accompanying drawings of the specification and it is embodied
Mode is described in detail the present invention.
As shown in Fig. 2, the present invention provides a kind of memory modules of Android embedded devices, including：Multiple memories
Grain slot 10, four groups of position configuration wire jumper 20 and the hardware interface 30 that is connect with CPU；Wherein, in being inserted into memory grain slot position 10
Particle is deposited, and the memory grain parameter (including capacity, working frequency, even-odd check etc.) being each inserted into is identical, four groups of configurations are jumped
Line 20 includes clock configuration wire jumper 21, capacity configuration wire jumper 22, address configuration wire jumper 23, power configuration wire jumper 24；
According to the memory grain parameter for being inserted into memory grain slot position 10, four groups of configuration wire jumpers 20 select to connect and it respectively
The corresponding configuration matched；This circuit configuration that former memory on board is adapted to by wire jumper, makes the circuit interface of memory and the circuit of CPU
Interface separates, the configuration variance of control signal, address pins that shielding memory grain is brought etc., the case where not changing circuit
Under, realize the compatible replacement between Android embedded device memory different models.
Embodiment one.
In the present embodiment, according to the memory grain parameter for being inserted into memory grain slot position 10, four groups of configuration wire jumpers 20 are distinguished
Matched corresponding configuration is connected in selection, specially：
Clock configures wire jumper 21, and being adapted to corresponding clock according to memory grain working frequency configures；
Capacity configuration wire jumper 22 always provides different capabilities configuration by insertion memory grain capacity；
Address configuration wire jumper 23 is adapted to corresponding address according to memory grain difference bit wide (8bit, 16bit, 32bit) and matches
It sets；
Power configuration wire jumper 24 is adapted to corresponding power configuration according to the operating voltage for being inserted into memory grain.
Embodiment two.
As shown in figure 3, a kind of memory modules of Android embedded devices provided in this embodiment connect with CPU it is hard
Part interface 30 is PIN pin forms, is inserted into Android embedded device corresponding interfaces by the PIN pins of definition and realizes the two
Between connection；Specifically, the memory modules of the present embodiment are the fixed dimension list formed by the PCB with 112 PIN pins
Plate, 112 PIN pins are arranged in obverse and reverse sides according to odd, even sequence crossover, and are defined to PIN pins.
Embodiment three.
In the present embodiment, PIN pins are specifically defined as respectively：
Data line DQ [31:0]；
Data strobe DQS [3:0]；
Data strobe complementation DQS# [3:0]；
Data mask [3:0]；
Clock signal CK；
Complementary clock signals CK#；
Clock enable signal CKE [1:0]；
Bank BA[2:0]；
Address wire A [15:0]
Column address strobe CAS；
Row address strobe RAS；
Write enabled WE；
On piece terminal coupling ODT [1:0]；
Piece selects CS [1:0]；
Reset RST；
Reference voltage VREF [1:0]；
Power vd D [3:0]；
Power ground VSS [7:0]；
Matching voltage VTT；
Clock configures wire jumper J1 [3:0]；
Capacity configuration wire jumper J2 [1:0]；
Address configuration wire jumper J3 [3:0]；
Address configuration wire jumper J4 [3:0]；
Other remaining PIN pins are that power supply, ground connection etc. assist pin.
Example IV.
As shown in figure 4, in the present embodiment, 10 quantity of memory grain slot position is four, can be inserted into memory grain number is 2n, n
0,1,2 are taken, the concrete configuration that four groups of configuration wire jumpers 20 provide is assigned as：
Clock configures wire jumper 21 and provides tetra- kinds of DDR3 400, DDR3 533, DDR3 667, DDR3 800MHz working frequencies
Configuration is adapted to corresponding clock from the configuration of above-mentioned working frequency according to memory grain working frequency and configures；
Capacity configuration wire jumper 22 provides tetra- kinds of capacity configurations of 512MB, 1GB, 2GB, 4GB, i.e., corresponding, is inserted into two
The schemes such as 256MB memory grains or a 512MB memory grain realize 512MB capacity, be inserted into four 256MB memory grains or
The schemes such as two 512MB memory grains of person or a 1GB memory grain realize 1GB capacity, are inserted into eight 256MB memory grains
Either the schemes such as four 512MB memory grains or two 1GB memory grains realize 2GB capacity, are inserted into 16 256MB memories
Either the schemes such as eight 512MB memory grains or four 1GB realize 4GB capacity to particle；Certainly, when memory grain slot position is more than
At four, it can be inserted into memory grain number and have more possibilities, the capability value for the memory modules that the present invention can provide can be more,
Correspondingly, realizing that the scheme of a capability value is also more, it can reach in the case where not changing main memory circuit, not according to reality
The quantity in stock of same parameter specification can be obtained the memory modules of identical capacity with Optional assembling, reach the memory of different designs parameter
The purpose flexibly replaced between chip particle, flexibility improve, and alternative costs reduce, and will not enumerate herein.
Address configuration wire jumper 23 provides row, column address line combination 12~16 row for the memory grain of different bit wides, 9~12 row
Address configuration；
Power configuration wire jumper 24 provides tri- kinds of typical supply voltage 1.2,1.35,1.6V power configurations, as be inserted into
The operating voltage of memory grain.
A kind of implementation method of the memory modules of Android embedded devices provided by the invention, includes the following steps：
Step S10, multiple memory grain slots position, four groups of configuration wire jumpers are set；
Step S20, according to Android embedded device memory bar demands, respective numbers are inserted into memory grain slot position
Memory grain, and memory grain parameter is identical；
Step S30, according to the memory grain parameter for being inserted into memory grain slot position, four groups of configuration wire jumpers select to connect respectively and
Its matched corresponding configuration.
In the present invention, four groups of configuration wire jumpers include clock configuration wire jumper, capacity configuration wire jumper, address configuration wire jumper, electricity
Source configures wire jumper；Specially：
Clock configures wire jumper, and being adapted to corresponding clock according to memory grain working frequency configures；
Capacity configuration wire jumper always provides different capabilities configuration by insertion memory grain capacity；
Address configuration wire jumper is adapted to corresponding address according to the different bit wides of memory grain；
Power configuration wire jumper is adapted to corresponding power configuration according to the operating voltage of memory grain.
The present invention matches by Android embedded device memory modules, and by the circuit of the former memory on board of wire jumper adaptation
It sets, the circuit interface of the circuit interface for making memory and CPU separates, control signal, the address pins etc. that shielding memory grain is brought
Configuration variance realize that compatibility between Android embedded device memory different models is replaced in the case where not changing circuit
It changes, simplifies the hardware design of complete machine, it is cost-effective, improve flexibility and production efficiency.
The invention is not limited in above-mentioned preferred forms, and anyone should learn that is made under the inspiration of the present invention
Structure change, the technical schemes that are same or similar to the present invention are each fallen within protection scope of the present invention.
Claims (10)
1. a kind of memory modules of Android embedded devices, which is characterized in that including：Multiple memory grain slots position, four assemble
The hardware interface set wire jumper and connect with CPU；
Wherein, the parameter for the memory grain for being inserted into memory grain in memory grain slot position, and being each inserted into is identical；
According to the memory grain parameter for being inserted into memory grain slot position, four groups of configuration wire jumpers selects matched corresponding of connection respectively
Configuration.
2. a kind of memory modules of Android embedded devices according to claim 1, which is characterized in that described four groups
Configuration wire jumper includes clock configuration wire jumper, capacity configuration wire jumper, address configuration wire jumper, power configuration wire jumper.
3. a kind of memory modules of Android embedded devices according to claim 2, which is characterized in that according to multiple
The configuration parameter of memory grain, four groups of configuration wire jumpers select to connect matched corresponding configuration respectively, specially：
Clock configures wire jumper, and being adapted to corresponding clock according to memory grain working frequency configures；
Capacity configuration wire jumper must be configured by insertion memory grain capacity to different capabilities；
Address configuration wire jumper, according to coming in and going out, memory grain difference bit wide is adapted to corresponding address configuration；
Power configuration wire jumper is adapted to corresponding power configuration according to the operating voltage for being inserted into memory grain.
4. a kind of memory modules of Android embedded devices according to claim 1, which is characterized in that described and CPU
The hardware interface of connection is PIN pin forms.
5. a kind of memory modules of Android embedded devices according to claim 4, which is characterized in that described and CPU
The PIN pins of the hardware interface of connection have 112.
6. a kind of memory modules of Android embedded devices according to claim 5, which is characterized in that the memory
Module be PCB formed fixed-size veneer, 112 PIN pins the veneer obverse and reverse sides according to odd, even sequence
Cross arrangement.
7. a kind of memory modules of Android embedded devices according to claim 5, which is characterized in that the PIN pipes
Foot is specifically defined as respectively：
Data line DQ [31:0]；
Data strobe DQS [3:0]；
Data strobe complementation DQS# [3:0]；
Data mask [3:0]；
Clock signal CK；
Complementary clock signals CK#；
Clock enable signal CKE [1:0]；
Bank BA[2:0]；
Address wire A [15:0]
Column address strobe CAS；
Row address strobe RAS；
Write enabled WE；
On piece terminal coupling ODT [1:0]；
Piece selects CS [1:0]；
Reset RST；
Reference voltage VREF [1:0]；
Power vd D [3:0]；
Power ground VSS [7:0]；
Matching voltage VTT；
Clock configures wire jumper J1 [3:0]；
Capacity configuration wire jumper J2 [1:0]；
Address configuration wire jumper J3 [3:0]；
Address configuration wire jumper J4 [3:0].
8. a kind of memory modules of Android embedded devices according to claim 2, which is characterized in that the memory
Particle number of slots amount is four, and pluggable memory grain quantity is 2n, n takes 0,1,2.
9. a kind of memory modules of Android embedded devices according to claim 8, which is characterized in that described four groups
The concrete configuration that configuration wire jumper provides is assigned as：
Clock configures wire jumper and provides DDR3 400, DDR3 533, DDR3 667, DDR3 800MHz tetra- for the memory grain being inserted into
Kind working frequency configuration；
Capacity configuration wire jumper provides tetra- kinds of capacity configurations of 512MB, 1GB, 2GB, 4GB to Android embedded devices；
Address configuration wire jumper provides row, column address line combination 12~16 row for the memory grain being inserted into, and the address of 9~12 row is matched
It sets；
Power configuration wire jumper provides tri- kinds of typical supply voltage 1.2,1.35,1.6V power configurations, as to be inserted into memory
The operating voltage of grain.
10. a kind of implementation method of the memory modules of Android embedded devices, which is characterized in that include the following steps：
Step S10, multiple memory grain slots position, four groups of configuration wire jumpers are set；
Step S20, it according to Android embedded device memory bar demands, is inserted into respective numbers in memory grain slot position
Particle is deposited, and memory grain parameter is identical；
Step S30, according to the memory grain parameter for being inserted into memory grain slot position, four groups of configuration wire jumpers select to connect and it respectively
The corresponding configuration matched；
Four groups of configuration wire jumpers include clock configuration wire jumper, capacity configuration wire jumper, address configuration wire jumper, power configuration wire jumper.
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| CN201810310030.0A CN108665916A (en) | 2018-04-09 | 2018-04-09 | A kind of memory modules and its implementation of Android embedded devices |
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| CN201810310030.0A CN108665916A (en) | 2018-04-09 | 2018-04-09 | A kind of memory modules and its implementation of Android embedded devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110162495A (en) * | 2019-05-27 | 2019-08-23 | 眸芯科技（上海）有限公司 | DDR adaptive approach and device |
| CN111104351A (en) * | 2019-12-19 | 2020-05-05 | 西安紫光国芯半导体有限公司 | Clock modulation method for memory module |
| CN116244119A (en) * | 2021-12-07 | 2023-06-09 | 深圳Tcl新技术有限公司 | Memory capacity identification method, device, smart device and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632762A (en) * | 2003-12-24 | 2005-06-29 | 上海华虹集成电路有限责任公司 | A smart card simulating card |
| CN101640066A (en) * | 2009-08-31 | 2010-02-03 | 曙光信息产业(北京)有限公司 | Memory controller and multi-memory system |
| US7990746B2 (en) * | 2005-06-24 | 2011-08-02 | Google Inc. | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies |
| CN107507637A (en) * | 2017-09-18 | 2017-12-22 | 深圳市江波龙电子有限公司 | A kind of low power consumption double-row In-line Memory and its enhancing driving method |
-
2018
- 2018-04-09 CN CN201810310030.0A patent/CN108665916A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632762A (en) * | 2003-12-24 | 2005-06-29 | 上海华虹集成电路有限责任公司 | A smart card simulating card |
| US7990746B2 (en) * | 2005-06-24 | 2011-08-02 | Google Inc. | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies |
| CN101640066A (en) * | 2009-08-31 | 2010-02-03 | 曙光信息产业(北京)有限公司 | Memory controller and multi-memory system |
| CN107507637A (en) * | 2017-09-18 | 2017-12-22 | 深圳市江波龙电子有限公司 | A kind of low power consumption double-row In-line Memory and its enhancing driving method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110162495A (en) * | 2019-05-27 | 2019-08-23 | 眸芯科技（上海）有限公司 | DDR adaptive approach and device |
| CN111104351A (en) * | 2019-12-19 | 2020-05-05 | 西安紫光国芯半导体有限公司 | Clock modulation method for memory module |
| CN116244119A (en) * | 2021-12-07 | 2023-06-09 | 深圳Tcl新技术有限公司 | Memory capacity identification method, device, smart device and storage medium |
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