CN104125164B - Active output buffer controller and method thereof - Google Patents

Abstract

The present invention provides an active output buffer controller and a method thereof. The active output buffer controller is used to control the packet data output of the main buffer in a network device, and the active output buffer controller includes a credit evaluation circuit and a control logic. The credit evaluation circuit estimates a credit value based on at least one of the inlet data receiving state of the network device and the outlet data transmitting state of the network device. The control logic compares the credit value with a first predetermined threshold value to generate a comparison result, and controls the packet data output of the main buffer at least according to the comparison result. The active output buffer controller and the method thereof provided by the present invention can avoid the occurrence of a first-in-first-out overflow.

Description

Active output buffer controller and method thereof

technical field

The present invention relates to an active output buffer controller and its method, in particular to an active output buffer controller and its method for actively controlling the packet data output of a main buffer in a network device.

Background technique

A network switch is a computer network device that can be used to connect different electronic devices. For example, a network switch receives input packets generated by a source electronic device connected to it, and only transmits output packets generated according to the received packets to one or more destination electronic devices specified by the received packets. Generally, a network switch has a main buffer (ie, a packet buffer) for buffering packet data of packets received by an ingress port, and forwards the packets stored in the main buffer through an egress port.

When the packet in the main buffer is ready to be forwarded to the egress port, the packet data will be loaded out from the main buffer through the egress pipeline to the FIFO in the media access control (media access control (MAC) layer device) (first-in first-out, FIFO) buffer, and then output to the physical layer device. Existing media access control layer devices require a larger FIFO buffer to prevent data overflow, resulting in an increase in chip size and cost. In addition, in order to prevent FIFO overflow, the MAC layer device will apply a backpressure mechanism to the main buffer controller to suspend the flow of packet data from the main buffer to the MAC layer device. First out buffer. The back pressure mechanism is activated when the FIFO buffer of the MAC layer device reaches a critical value. However, there will be a time gap between starting the back pressure mechanism and starting the back pressure program. Moreover, after the back pressure mechanism suspends outputting packet data from the main buffer, some data in the egress pipeline will still enter the FIFO buffer of the MAC layer device. Therefore, it is still possible to overflow the FIFO buffer even with the back pressure mechanism.

Contents of the invention

The invention relates to an active output buffer controller and its method.

According to the first embodiment of the present invention, an active output buffer controller is provided for controlling the packet data output of a main buffer in a network device, the active output buffer controller includes a credit evaluation circuit and a control logic. The credit evaluation circuit estimates a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device. The control logic compares the credit value with a first predetermined threshold to generate a comparison result, and controls the packet data output of the main buffer at least according to the comparison result.

According to a second embodiment of the present invention, a method for controlling packet data output of a primary buffer is provided. The primary buffer is located in a network device, and the method of controlling packet data output of the primary buffer includes: estimating a credit value based on at least one of an ingress data receiving status of the network device and an egress data transmission status of the network device; and comparing the credit value with a first predetermined threshold to generate a comparison result; and controlling the packet data output of the main buffer at least according to the comparison result.

The active output buffer controller and method thereof proposed by the present invention can avoid the occurrence of FIFO overflow.

Description of drawings

FIG. 1 is a schematic diagram of a network device using an active output buffer control mechanism according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an embodiment of the active output buffer controller shown in FIG. 1 .

FIG. 3 is a schematic diagram of corrective operations triggered by a backpressure event according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a correction operation triggered by a deviation event according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a correction operation triggered by a time-up event according to an embodiment of the present invention.

FIG. 6 is a flow chart of a method for controlling packet data output of a primary buffer in a network device according to an embodiment of the present invention.

detailed description

Certain terms are used throughout the specification and preceding claims to refer to particular elements. Those of ordinary skill in the art should understand that hardware manufacturers may use different terms to refer to the same component. The description and the preceding claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. "Includes" mentioned throughout the specification and the preceding claims is an open-ended term, so it should be interpreted as "including but not limited to". Otherwise, the term "coupled" includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

The technical feature of the present invention is to actively control the data storage status of the first-in-first-out (FIFO) buffer of the media access control (media access control, MAC) layer device, and actively control the network device. Packet data output from primary buffers such as packet buffers in network switches/hubs. In this way, the FIFO overflow situation can be predicted in advance and avoided by the proposed active output buffer control mechanism. Preferably, the proposed active output buffer control mechanism can be combined with the existing back pressure mechanism to provide a better FIFO overflow prevention method for the MAC layer device. In addition, a calibration mechanism can be used to align the estimated credit value (i.e. the predicted data storage status of the FIFO of the MAC layer device) with the actual data of the FIFO buffer of the MAC layer device Stored states are synchronized with each other. Further details about the proposed active output buffer control mechanism are detailed below.

FIG. 1 is a schematic diagram of a network device using an active output buffer control mechanism according to an embodiment of the present invention. In this embodiment, the network device 100 is a switch/hub, including a main buffer (such as a packet buffer) 102, a main buffer controller 104, an egress pipeline 106, a media with a first-in-first-out buffer 107 The access control layer device 108 , the physical layer device 110 and the active output buffer controller 112 . The egress pipeline 106, the MAC layer device 108, and the physical layer device 110 are used to forward packets only through the egress port. The main buffer 102 can receive ingress packets through an ingress pipeline (not shown), and store a packet cell 103 for each ingress packet in a plurality of available storage spaces available in the main buffer 102 . In the standard mode, the packet cell is regarded as the basic unit output by the main buffer 102 in each clock cycle. That is to say, if the packet data output of the main buffer 102 does not suspend the action to avoid encountering the situation of first-in first-out overflow when the packet data is forwarded through the egress port, the main buffer controller 104 will control the main buffer 102 in each The clock cycle outputs the packet cells to the egress pipeline 106 . The outlet pipeline 106 is coupled between the main buffer 102 and the FIFO buffer 107 . Therefore, even if the main buffer 102 stops its packet data output action of forwarding packets through the egress port, the egress pipeline 106 may still have packet cells in it, and these packet cells will be sequentially output to the first-in-first-out Buffer 107. The physical layer device 110 is coupled between the egress port and the MAC layer device 108 for outputting the packet cells in the FIFO buffer 107 to the egress port.

In this embodiment, the active output buffer controller 112 is an independent engine externally coupled to the main buffer controller 104, thus providing an external control signal S_C to the main buffer controller 104 to actively control by instructing the main buffer controller 104 Packet data output from main buffer 102 . However, the above is for illustrative purposes only, and is not intended to limit the present invention. In other variant designs, the active output buffer controller 112 can be integrated into the main buffer controller 104 to form an embedded function of the main buffer controller 104, and thus provide control signals to actively control the packet data output of the main buffer 102 . In another design variation, the active output buffer controller 112 may be integrated with circuit components other than the active output buffer controller 112 (such as the egress pipeline 106 or the MAC layer device 108) and thus provide external control The signal S_C is sent to the main buffer controller 104 to actively control the packet data output of the main buffer 102 by instructing the main buffer controller 104 . In short, the proposed active output buffer control mechanism can be implemented in network devices as long as the purpose is to achieve the same purpose, that is, to actively control the packet data output action of the main buffer related to packet forwarding through the egress port. 100, and all belong to the scope of rights of the present invention.

As shown in FIG. 1 , the active output buffer controller 112 includes but is not limited to a credit evaluation circuit 122 , a control logic 124 and a correction circuit 126 . The credit evaluation circuit 122 is the core circuit of the active output buffer controller 112 and is used for predicting the data storage status of the FIFO buffer 107 in the MAC layer device 108 . For example, the active output buffer controller 112 (eg, the credit evaluation circuit 122 ) can estimate the credit value SUM based on at least one of the ingress data receiving state S1 of the network device 100 and the egress data transmission state S2 of the network device 100 . According to another embodiment of the present invention, the active output buffer controller 112 (for example, the credit evaluation circuit 122) may be based on the implementation specification S3, and the ingress data receiving state S1 of the network device 100 and the egress data transmission state S2 of the network device 100 At least one of the credit value SUM is estimated.

For example, but the present invention is not limited thereto. The implementation specification S3 includes at least one of the packet cell size, the operating frequency of the MAC layer device 108 , and the time-division multiplexing (TDM) period of the egress port. More specifically, the packet cell size represents the number of characters/bits in each packet cell output from the main buffer 102 within a clock cycle. The TDM cycle of the egress port determines the number of clock cycles between two consecutive TDM slots in which a transfer from the main buffer 102 to the egress pipeline 106 is performed. Packet data transfer. The operating frequency of the MAC layer device 108 determines the egress in the TDM cycle. In addition to the parameters mentioned above, the implementation specification S3 may also contain other parameters.

By way of example, but not limitation. The ingress data receiving state S1 may include at least one of ingress data incoming rate, ingress packet forwarding method, and ingress pipeline depth. More specifically, the ingress data rate indicates how many ingress packet characters/bits the network device 100 can receive in each clock cycle. The ingress packet forwarding method defines how to control packet forwarding. For example, a store-and-forward (SF) method or a cut-through (CT) method may be used to forward the ingress packet depending on practical considerations. The ingress pipeline depth specifies the maximum number of ingress packet cells that the ingress pipeline can hold. In addition to the parameters mentioned above, the entry data receiving state S1 may also contain other parameters.

By way of example, but not limitation. The egress data transmission state S2 may include at least one of egress pipeline depth, FIFO size of the MAC layer device 108 , transmission rate of the physical layer device 110 , and egress packet size change information. More specifically, the egress pipeline depth specifies the maximum number of egress packet cells that can be accommodated by the egress pipeline 106 . The FIFO size of the MAC layer device 108 specifies the maximum number of egress packet cells that the FIFO buffer 107 can hold. The transmission rate of the physical layer device 110 indicates how many egress packet characters/bits are sent by the physical layer device 110 per clock cycle. The egress packet size change information defines the size of the additional information added to the egress packet data when the egress packet data is sent from the main buffer 102 to the physical layer device 110; and/or when the egress packet data is sent from the main buffer 102 to the physical layer device 110; Size of auxiliary information removed from egress packet data when layer device 110 is used. In addition to the parameters mentioned above, the egress data transfer state S2 may also contain other parameters.

The estimated credit value SUM represents the predicted data storage status of the FIFO buffer 107 in the MAC layer device 108 . In an exemplary design, the credit value SUM may be the predicted number of packets in the FIFO buffer 107 . In another exemplary design, the credit value SUM may be the number of predicted characters, half characters or 1/4 characters in the FIFO buffer 107 . In addition, for different operations performed by the MAC layer device 108, the credit value SUM may correspond to different weights. For example, the MAC layer device 108 will duplicate the packing (packer)/package cell under the multicast operation, therefore, under the operation of the current MAC layer device 108, adjust the credit value SUM to reflect the actual The usage status of the FIFO buffer.

The control logic 124 is used for comparing the credit value SUM with a predetermined threshold TH1 to generate a comparison result CR, and setting the control signal S_C to control the packet data output of the main buffer 102 at least according to the comparison result CR. For example, when the comparison result CR indicates that the credit value SUM reaches the predetermined critical value TH1, the control logic 124 will judge that the available space in the FIFO buffer 107 cannot meet the minimum safety margin, and FIFO overflow may occur status. Therefore, the control logic 124 will enable the control signal S_C (assert) (for example, the control signal S_C=1) to control the main buffer controller 104 to suspend the packet data output of the main buffer 102 . After the packet data output of the main buffer 102 is suspended, the first-in-first-out buffer 107 will slowly release the occupied space by outputting the stored packet data to the secondary circuit (i.e., the physical layer device 110), and correspondingly Update the credit value SUM accordingly. When the credit value SUM drops to a lower level, the control logic 124 will determine that the FIFO buffer 107 has escaped the threat of unnecessary memory overflow. Then, the control logic 124 deasserts the control signal S_C (for example, the control signal S_C=0) to control the main buffer controller 104 to restart the packet data output of the main buffer 102, so as to allow new packet cell data to come through the output port. Forward it.

Please refer to FIG. 2 , which is a schematic diagram of an embodiment of the active output buffer controller 112 shown in FIG. 1 . The aforementioned parameters such as the ingress data receiving state S1, the egress data transmission state S2, and the implementation specification S3 are combined with the credit value obtained from the last TDM time slot. It should be noted that, based on the definition of the parameters, one or more parameters can apply the increment (increment) of the credit value obtained from the last TDM time slot, and/or one or more parameters can apply the increment (increment) from the last TDM time slot. The decrement of the credit value obtained by the time slot. The control logic 124 checks the finally obtained credit value SUM to set the control signal S_C.

When the credit value SUM does not exceed the safety range, the packet cell data character count will update the credit value SUM, and then store the credit value SUM back to the port record as the credit value obtained from the last TDM time slot. However, when the credit value SUM exceeds the security range (or if the MAC layer device adopts the back pressure mechanism and a back pressure event occurs), the packet cell data character count will not update the credit value SUM, but directly Store the credit SUM back to the port record as the credit obtained from the last TDM slot.

In addition, for the end of a packet (end of a packet, EOP), the media access control layer device 108 can attach additional characters to the packet to separate the packet from the next packet; and for the beginning of the packet (start of a packet, SOP), since the auxiliary character is only used to provide the auxiliary information of the media access control layer device 108, and will not be forwarded to the destination electronic device through the output port, the media access control layer device 108 can Remove auxiliary characters from the header of the packet. Therefore, the packet cell data character count for the current TDM slot can be properly adjusted according to the above details.

As mentioned above, when the comparison result CR shows that the credit value SUM reaches the predetermined threshold value TH1, the control logic 124 will activate the control signal S_C to instruct the main buffer controller 104 to suspend the packet data output of the main buffer 102, so that new incoming packets cannot Enters the outlet line 106 and forwards through the outlet port. Rather than suspending the packet data output of the main buffer 102 at the boundary of the packet to be forwarded, the control logic 124 controls the packet data output of the main buffer 102 to suspend at the boundary of the packet cell in the packet to be forwarded. That is, when packet data output is paused, the main buffer 102 is allowed to output one or more packet cells in the packet to Outlet line 106. In this way, the egress pipeline and FIFO buffer can be used more efficiently to provide better egress throughput. In the case that the output pipeline and the FIFO buffer support higher granularity, when the comparison result CR shows that the credit value SUM reaches a predetermined critical value TH1, the control logic 124 will control the packet data output of the main buffer 102 to suspend at the desired level. On the boundary of a part of the packet cell in the forwarded packet. In addition, when the comparison result CR shows that the credit value SUM has not reached the first predetermined threshold TH1, the control logic 124 further generates a check result by checking whether the MAC layer device 108 makes the back pressure signal S_BP effective, and according to the check result, Control the packet data output of the main buffer 104 .

As mentioned above, the credit value SUM is obtained by predicting the data storage state of the first-in-first-out buffer 107 in the MAC layer device 108. The credit value SUM of the predicted data storage status may deviate from the actual data storage status of the FIFO buffer 107 in the MAC layer device 108 . In the worst case, when the FIFO buffer 107 is almost full of data, the credit value SUM may be much lower than the predetermined threshold value TH1. In order to avoid such a situation, the media access control layer device 108 adopts a back pressure mechanism to monitor the actual data storage status of the first-in first-out buffer 107 in the media access control layer device 108, and when the first-in first-out buffer 107 When the actual number of data stored in reaches a predetermined threshold TH _BP , the back pressure signal S_BP becomes effective. Therefore, when the control logic 124 considers that the credit value SUM has not reached the predetermined threshold TH1, the control logic 124 further confirms whether the MAC layer device 108 asserts the back pressure signal S_BP. When the credit value SUM shows that the predetermined threshold value TH1 is not reached, but the back pressure signal S_BP is asserted, the control signal S_C still controls the main buffer controller 104 to suspend the packet data output of the main buffer 102 .

Preferably, the present invention further proposes a correction mechanism to avoid/relieve problems caused by misestimation of the credit value SUM. Specifically, when the specific event TRG is triggered, the correction circuit 126 corrects the credit value SUM based on the actual number of data in the FIFO buffer 107 in the MAC layer device 108 . For example, the correction circuit 126 corrects the credit value SUM by synchronizing the credit value SUM with the actual data amount of the FIFO buffer 107 . That is, the actual data volume in the FIFO buffer 107 is used to readjust the credit value SUM. Several embodiments of the correction mechanism of the present invention are provided below.

In a first exemplary correction design, the correction circuit 126 corrects the credit value SUM in response to the backpressure signal S_BP asserted by the MAC layer device 108 . In other words, the specific event TRG is a back pressure event triggered when the MAC layer device 108 activates the back pressure mechanism to prevent the FIFO buffer from overflowing. Please refer to FIG. 3 , which is a schematic diagram of a calibration operation triggered by a back pressure event according to an embodiment of the present invention. The characteristic curve CV1 is used to represent the actual data volume of the FIFO buffer 107 in the MAC layer device 108 , and the characteristic curve CV2 is used to represent the credit value SUM estimated and recorded by the active output buffer controller 112 . Since the proposed active buffer control mechanism has a more rigorous attitude towards FIFO overflow evaluation (that is, the proposed active buffer control mechanism tends to underestimate the credit value), it will lead to the estimated credit value SUM and the media There is a mismatch between the actual data volumes of the FIFO buffer 107 in the access control layer device 108 . In this embodiment, the credit value SUM is accumulated at a slower speed, and the actual data amount of the FIFO buffer 107 is accumulated at a faster speed. In this way, the back pressure event may be triggered before the credit value SUM reaches the predetermined threshold value TH1. As shown in FIG. 3 , at time T1, the amount of data in the FIFO buffer 107 reaches a predetermined threshold TH _BP . Therefore, the MAC layer device 108 asserts the back pressure signal S_BP, so that the correction circuit 126 is triggered by a specific event (ie, a back pressure event) TRG.

When the back pressure procedure is activated, the packet data output from the main buffer 102 to the output port will be suspended. However, the FIFO buffer 107 will still work normally to output the packet data to the physical layer device 110, so the data volume of the FIFO buffer 107 will gradually decrease. When the amount of data in the FIFO buffer 107 drops to a specific value BP _OFF at time T2, the MAC layer device 108 will deassert the back pressure signal S_BP to turn off the back pressure mechanism, thereby allowing the main buffer 102 resumes output of its packet data.

After being triggered by a specific event TRG, the correction circuit 126 determines that the credit value SUM is synchronized with the data amount in the FIFO buffer 107 at time T2 (ie, the time point when the packet data output of the main buffer 102 is restored). In this embodiment, the calibration circuit 126 immediately sets the credit value SUM to a specific value BP _OFF at time T1, and then maintains the credit value SUM until the back pressure mechanism is released at time T2. Therefore, at time T2, the credit value SUM is readjusted with the actual amount of data in the FIFO buffer 107 . It should be noted that the embodiment in FIG. 3 is not intended to limit the present invention. For example, the correction circuit 126 can set the credit value SUM to a specific value BP _OFF at any time point between time T1 and time T2 , and then keep the credit value SUM until the back pressure mechanism is released at time T2 . The purpose of synchronizing the credit value SUM with the actual data amount in the FIFO buffer 107 can also be achieved.

In the second exemplary calibration design, the calibration circuit 126 further monitors the difference between the credit value SUM and the actual data volume of the FIFO buffer 107 in the MAC layer device 108 . For example, the calibration circuit 126 can use a software module (ie monitoring software) or a hardware module (eg monitoring device) to check whether the difference reaches the predetermined threshold TH2. When the difference reaches a predetermined threshold TH2, it means that the credit value SUM should be adjusted to keep its pace consistent with the actual data volume in the FIFO buffer 107 , and a specific event TRG is triggered to enable the correction circuit 126 .

Please refer to FIG. 4 , which is a schematic diagram of a correction operation triggered by a deviation event according to an embodiment of the present invention. The characteristic curve CV1 represents the data amount of the FIFO buffer 107 in the MAC layer device 108 , and the characteristic curve CV2 is used to represent the credit value SUM estimated and recorded by the active output buffer controller 112 . As mentioned above, since the proposed active buffer control mechanism has a more rigorous attitude towards FIFO overflow evaluation, the estimated credit value SUM and the FIFO buffer in the media access control layer device 108 There is a mismatch between the actual data volume of 107. In this embodiment, the credit value SUM is accumulated at a slower speed, and the actual data amount of the FIFO buffer 107 is accumulated at a faster speed. The difference between the credit value SUM and the actual amount of data in the FIFO buffer 107 will gradually increase. At time T1, the difference D1 between the credit value SUM and the actual data volume of the FIFO buffer 107 has not yet reached the predetermined critical value TH2, so there is no need to correct the credit value SUM so that it is synchronized with the actual data volume of the FIFO buffer 107. The amount of data. However, at time T2, the monitoring program/monitoring device of the correction circuit 126 will detect that the difference D2 between the credit value SUM and the actual data amount of the FIFO buffer 107 has reached a predetermined threshold TH2, so the specific event ( That is, a deviation event) will trigger the specific event TRG correction circuit 126 to correct the credit value SUM, so the actual data amount of the FIFO buffer 107 can be used to readjust the credit value SUM.

In the third exemplary correction design, the correction circuit 126 corrects the credit value SUM when a predetermined timing condition is met. For example, but the present invention is not limited thereto. The correction circuit 126 may periodically correct the credit value SUM. For example, the calibration circuit 126 may use a software module (ie, monitoring software) or a hardware module (eg, a monitoring device) to count a predetermined period of time T, and trigger a time-out event when the time meets the predetermined period of time T. In other words, when the time meets the predetermined period of time T, it means that the credit value SUM should be adjusted immediately, and the specific event TRG is triggered to enable the correction circuit 126 . Please refer to FIG. 5 , which is a schematic diagram of a correction operation triggered by a time-out event according to an embodiment of the present invention. The characteristic curve CV1 represents the data amount of the FIFO buffer 107 in the MAC layer device 108 , and the characteristic curve CV2 is used to represent the credit value SUM estimated and recorded by the active output buffer controller 112 . As mentioned above, since the proposed active buffer control mechanism has a more rigorous attitude towards FIFO overflow evaluation, the estimated credit value SUM and the FIFO buffer in the media access control layer device 108 There is a mismatch between the actual data volume of 107. In this embodiment, the credit value SUM is accumulated at a slower speed, and the actual data amount of the FIFO buffer 107 is accumulated at a faster speed. The time T1 , time T2 and time T3 respectively satisfy the predetermined period of the time T, therefore, the correction circuit 126 periodically triggers a specific event TRG (ie, time-up event) to correct the credit value SUM. Therefore, the credit value SUM can be readjusted at the time T1 , the time T2 and the time T3 respectively by using the actual data amount of the FIFO buffer 107 .

In the above examples shown in FIG. 4 and FIG. 5 , the credit value SUM is accumulated at a slower speed, and the actual data amount of the FIFO buffer 107 is accumulated at a faster speed. However, this is for illustrative purposes only, and the present invention is not limited thereto. In fact, the gap between the credit value SUM and the actual data volume of the FIFO buffer 107 cannot be known in advance. That is to say, the estimated credit value SUM may be smaller than the actual data volume of the FIFO buffer 107 at a certain time point, and may be larger than the actual data volume of the FIFO buffer 107 at another time point. Therefore, the adjustment of the estimated credit value SUM by the correction circuit 126 can be increased or decreased, depending entirely on the relationship between the estimated credit value SUM and the actual data volume of the FIFO buffer 107 .

FIG. 6 is a flow chart of a method for controlling packet data output of a primary buffer in a network device according to an embodiment of the present invention. If substantially the same result can be achieved, it is not necessary to follow the order of the steps in the process shown in Figure 6, and the steps shown in Figure 6 do not have to be performed continuously, that is, other steps can also be inserted therein, in addition, Certain steps in FIG. 6 may also be omitted according to different embodiments or design requirements. This exemplary method can be applied to the active output buffer controller 112 shown in FIG. 1, and the method is briefly summarized as follows:

Step 600: start;

Step 602: Estimate a credit value based on at least one of an ingress data receiving status of the network device and an egress data transmission status of the network device. In some designs of the invention, an estimate of the credit value may refer to an implementation specification.

Step 604: Check whether the credit value reaches a predetermined threshold. If yes, go to step 610 ; otherwise, go to step 606 .

Step 606: Check whether the back pressure signal is valid. If yes, go to step 610 ; otherwise, go to step 608 .

Step 608: Allow the primary buffer to generate packet data output to the egress pipeline. Go to step 612 .

Step 610: Control the main buffer to suspend the output of the packet data to the egress pipeline.

Step 612: Check whether there is a specific event of credit value correction. If yes, go to step 614 ; otherwise, go to step 616 .

Step 614: Correct the credit value based on the actual data volume of the FIFO buffer of the MAC layer device. For example, the credit value is corrected by synchronizing the credit value with the actual data volume of the FIFO buffer of the MAC layer device.

Step 616: end.

Since those skilled in the art should easily understand the details of each step after reading the above content, further description is omitted here for brevity.

It should be noted that the active output buffer controller 112 in FIG. 1 and the related method in FIG. 6 are for illustration purposes only, and are not intended to limit the present invention. That is, the active output buffer controller 112 in FIG. 1 and the related method in FIG. 6 can be modified without departing from the spirit of the present invention. For example, the back pressure mechanism in the MAC layer device 108 can be omitted. In this way, the active output buffer controller 112 sets the control signal S_C based on the credit value SUM instead of referring to the back pressure signal S_BP. As another example, the correction circuit 126 in the active output buffer controller 112 can be omitted. Therefore, the active output buffer controller 112 is changed to set the control signal S_C based on the credit value SUM without corrective operation. Such changes and designs all belong to the right scope of the present invention.

By using the proposed active output buffer controller, a higher FIFO utilization can be obtained by properly controlling the packet data transfer between the MAC layer device and the main buffer. In addition, since the proposed active output buffer controller can actively avoid the first-in first-out overflow situation of the media access control layer device, the back pressure mechanism can also be omitted to reduce the complexity of routing (routing), and /or reduce the size of the FIFO in the MAC layer device to save cost.

Although the present invention has been disclosed above with preferred embodiments, it should be understood that it is not intended to limit the present invention. On the contrary, any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be defined by the claims.

Claims (22)

1. An active output buffer controller, characterized in that, the active output buffer controller is used to control the packet data output of the main buffer in the network device, and the active output buffer controller includes: a credit evaluation circuit estimating a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device; a control logic that compares the credit value with a first predetermined threshold to generate a comparison result, and controls the packet data output of the primary buffer at least according to the comparison result; and A correction circuit for correcting the credit value based on the actual amount of data in the first-in-first-out buffer of the media access control layer device; Wherein the calibration circuit corrects the credit value in response to the back pressure signal activated by the MAC layer device; and when the MAC layer device does not validate the back pressure signal, the calibration circuit does not correct the credit value. 2. The active output buffer controller according to claim 1, wherein when estimating the credit value, the credit evaluation circuit further refers to an implementation specification. 3. The active output buffer controller according to claim 2, wherein the implementation specification includes packet cell size, the operating frequency of the media access control layer device, and the TDM cycle of the output port at least one. 4 . The active output buffer controller according to claim 1 , wherein the ingress data receiving status includes at least one of ingress data incoming rate, ingress packet forwarding method, and ingress pipeline depth. 5. The active output buffer controller according to claim 1, wherein the egress data transfer status includes egress pipeline depth, FIFO size of MAC layer devices, transfer rate of physical layer devices, and At least one of the egress packet size change information. 6. The active output buffer controller according to claim 1, wherein when the comparison result shows that the credit value reaches the first predetermined threshold, the control logic suspends the output of the packet data of the main buffer Packet Cell Boundary in the packet to be forwarded. 7. The active output buffer controller according to claim 1, wherein when the comparison result shows that the credit value reaches the first predetermined critical value, the control logic suspends the output of the packet data of the main buffer The boundary of a portion of a Packet Cell in a packet to be forwarded. 8. The active output buffer controller according to claim 1, wherein when the comparison result shows that the credit value has not reached the first predetermined critical value, the control logic further checks whether the media access control layer device The back pressure signal is enabled to generate a check result, and the packet data output of the main buffer is controlled according to the check result. 9. The active output buffer controller according to claim 1, wherein the correction circuit corrects the credit value. 10. The active output buffer controller according to claim 1, wherein the correction circuit further monitors the relationship between the credit value and the actual data volume of the FIFO buffer of the MAC layer device difference; and when the difference reaches a second predetermined threshold, the correction circuit corrects the credit value. 11. The active output buffer controller according to claim 1, wherein the correction circuit corrects the credit value when a predetermined timing condition is met. 12. A method for controlling the output of packet data of a main buffer, characterized in that, the main buffer is located in a network device, and the method for controlling the output of packet data of the main buffer comprises: estimating a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device; comparing the credit value with a first predetermined threshold to generate a comparison result; controlling the packet data output of the primary buffer at least according to the comparison result; and correcting the credit value based on an actual amount of data in the FIFO buffer of the MAC layer device; Wherein the credit value is corrected in response to the back pressure signal activated by the MAC layer device; and the credit value is not corrected when the back pressure signal is not valid by the MAC layer device. 13. The method for controlling the packet data output of the main buffer according to claim 12, wherein the step of estimating the credit value further comprises: When estimating this credit value, refer to the implementation specification. 14. The method for controlling the packet data output of the main buffer according to claim 13, wherein the implementation specification includes the packet cell size, the operating frequency of the media access control layer device, and the time-sharing of the output port At least one of the multitasking cycles. 15. The method for controlling the packet data output of the main buffer according to claim 12, wherein the ingress data receiving status includes at least one of ingress data incoming rate, ingress packet forwarding method, and ingress pipeline depth . 16. The method for controlling the packet data output of the main buffer according to claim 12, wherein the egress data transfer status includes the egress pipeline depth, the first-in-first-out size of the media access control layer device, and the physical layer device At least one of the transmission rate and the egress packet size change information. 17. The method for controlling the packet data output of the main buffer according to claim 12, wherein the step of controlling the packet data output of the main buffer comprises: When the comparison result shows that the credit value reaches the first predetermined threshold, the packet data output of the main buffer is suspended at the boundary of the packet cell in the packet to be forwarded. 18. The method for controlling the packet data output of the main buffer according to claim 12, wherein the step of controlling the packet data output of the main buffer comprises: When the comparison result shows that the credit value reaches the first predetermined threshold, the output of the packet data from the primary buffer is suspended at the boundary of a portion of packet cells in the packet to be forwarded. 19. The method for controlling the packet data output of the main buffer according to claim 12, wherein the step of controlling the packet data output of the main buffer comprises: When the comparison result shows that the credit value does not reach the first predetermined threshold, a check result is generated by checking whether the MAC layer device makes a back pressure signal effective, and controlling the main buffer according to the check result The packet data is output. 20. The method for controlling the packet data output of the main buffer according to claim 12, wherein the step of correcting the credit value comprises: The credit value is corrected by synchronizing the credit value with the actual data size of the FIFO buffer of the MAC layer device. 21. The method for controlling the packet data output of the main buffer according to claim 12, wherein the step of correcting the credit value comprises: monitoring the difference between the credit value and the actual data volume of the FIFO buffer of the MAC layer device; and The credit value is corrected when the difference reaches a second predetermined threshold. 22. The method for controlling the packet data output of the main buffer as claimed in claim 12, wherein the credit value is corrected when a predetermined timing condition is met.