CA1165465A - Over/under dual in-line chip package - Google Patents
Over/under dual in-line chip packageInfo
- Publication number
- CA1165465A CA1165465A CA000370651A CA370651A CA1165465A CA 1165465 A CA1165465 A CA 1165465A CA 000370651 A CA000370651 A CA 000370651A CA 370651 A CA370651 A CA 370651A CA 1165465 A CA1165465 A CA 1165465A
- Authority
- CA
- Canada
- Prior art keywords
- wafer
- intra
- level
- wafers
- conductive strips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Dram (AREA)
Abstract
Abstract:
The present invention relates to an electronic circuit package for encapsulating and interconnecting two or more semiconductor chips. A vertically stacked array of sub-strate wafers form a support core in which windows are formed for receiving the chips. Device support surfaces and device lead connecting surfaces are exposed by each cavity on one or more of the substrate wafers. Intra-level conductive strips are separately deposited on each lead connecting surface for attachment to the input/output leads of the circuit devices and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins. Inter-level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra-level conductive strips of a different level. In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement.
The present invention relates to an electronic circuit package for encapsulating and interconnecting two or more semiconductor chips. A vertically stacked array of sub-strate wafers form a support core in which windows are formed for receiving the chips. Device support surfaces and device lead connecting surfaces are exposed by each cavity on one or more of the substrate wafers. Intra-level conductive strips are separately deposited on each lead connecting surface for attachment to the input/output leads of the circuit devices and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins. Inter-level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra-level conductive strips of a different level. In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement.
Description
I ~ 65465 OVI~RjUNDER DU~L IN-LINE CHIP PACI~GE
BAC~GROUND OF THE INVENTlON
Field of the Invention:
The present invention relates generally to electronic packaging, and particularly to inter-layer and intra-layer connecting means for multi-chip modules.
5 Description of the Prior Art:
The packaging of electronic equipment has become a major factor in the design and manufacture of contemporary electronic systems. New packaging techniques are required to meet the demand for reduced physical size and improved reliability at lower cost. The problem of efficient packaging is 10 particularly important ir~ electronic circuits which utilize microcircuit structures of the type implemented by LSI techniques on a semiconductor substrate chip.
Conventional electronic circuit packages for semiconductor chips are adapted to enclose and hermetically seal the chip devices, while also 15 providing heat dissipation, structural support, electrical attachment of device leads to external pin connectors, and electrical interconnection with other devices in the package. Such packages are usually formed of one or more layers of a non-conductive substrate waf er, with a central cavity in which the semiconductor chip is received. Flexible metal leads are extended between the 20 layers to the central cavity for connection with the device input/output leads.
Because of industry standards relating to the exterior dimensions for electroniccircuit packages, including spacing between leads and between lead rows in the "~
" _ _ ,~
__,. __ , ~ . . __ . _ .. . . . . .
` ` ` ` I J 65465 case of the standard dual in-line package, the presence of multiple flexible metal leads has limited the number of circuit devices which can be encapsulated in a standard package.
There is a continuing interest in increasing the device packaging density, particularly for semiconductor memory circuitry used in high speed 5 data processing circuits, for example random access memory (RAM) circuits implemented by MOS/LSI techniques on semiconductor substrate.chips. One particular industry package standard for memory devices specifies 300 mil row spacing with external pins mounted on 100 mil cènters in each row. I~lemory capacity for this standard package can be upgraded from a pair of 81~ bit R~M
10 devicesJ to a pair of 16K bit RAM devices, or to a pair of 64K bit RAM devices.
As the memory capacity of the chips becomes largerJ the chip substrate area required to implement the increased memory is also increased, thereby reducing to a minimum the area available for the device lead attachment within a package having standard dimensions. Accordingly, various 15 attempts have been made to redesign the package in order to provide a larger chip cavity. It will be appreciated that the mounting area available for the device substrate, for a given standard package, is necessarily limited by the space required for device lead bonding and by the minimum dimensions necessary to provide a hermetic seal. The conventional dual chip, in-line 20 packaging assembly has~resulted because of the memory substrate area constraint and has doubled memory capacity while conforming with lead row standards. Although memory capacity may be increased by adding additional memory chips in tandem, in-line relation with the standard dual chip in-line configuration, because of established standards for lead center spacing and 25 maximum number of external pins and package length, such arrangements have not achieved widespread acceptance. Therefore there is a serious and continuing need for an improved electronic circuit package in which the device density can be s~bstantially increased while conforming with established industry packaging standards.
SUMMARY OF OBJECTS OF THE INVENTION
Accordingly, the principal object of the present invention is to _ ~ 1 654~5 provide an clectronic circuit paclcage having n substantiaUy increnscd device packagillg density which conforms with established standards.
A rel~ted object is to provide an electronic circuit package for encapsulating and interconnecting multiple semiconductor chips.
Another object of the invelltion is to provide an electronic circuit S package for encapsulating and interconnecting four identical semiconductor chips for multiplex operation.
Yet another object of the invention is to provide a~ electronic circuit package for encapsulating and interconnecti;Ig mlùtiple pairs of semiconductor circuit devices in an over/under, dual chip in-line arrangement in10 which each chip device may be operated independently of the other chip devices on a multiplex basis with only a minimum number of external connector pins.
SVMMARY OF THE INVENTION
The foregoing objects are realized by a vertically stacked array of 15 substrate wafers which form a support core in which windows are formed for separately receiving an~ mounting semiconductor chip circuit devices. Device support surfaces and device lead connecting surfaces are exposed by each window on one or more of the substrate wafers. Intra-level conductive strips are separately disposed on each lead connecting surface for attachment to the 20 input/output leads of each semiconductor chip and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins Inte~level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra-level conductive strips of a different level.
In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement. In this arrangement, two RAM chips are mounted n~ in^
line relation on a common substrate wafer at an upper level, and two RAM chips are mounted on a common substrate wafer at a lower level. Corresponding data and power terminals of the chips on the upper level are interconnected in common with each other and to a common external pin by the combination of intra-level conductive strips extending through the interface of adjacent wafer substrates at first and second levels, and by inter-level conductive 65~65 intercomlects which intersect nnd nre clllbeddc~ in the substr-ltc wnl`er on whicll the de~icc leads nre bondcd. Idellticnl powcr alld data tcrmill~ùs o~ th~ lower R~M cllips are similarly intercomlected with each other and are interconnected with the correspondil-g data nnd power terminals of the upper R~l cllipS by an intermediate group of intrfl-level conductive strips and by inte~level 5 conductive interconnects which intersect the substrate wafers which form the interface along which the intermediate group of intra-level conductive strips are disposed.
The novel features which chnracterize the invention are defined by the appended claims The foregoin~ and other objects, advantnges and fefltures 10 of the invention will hereinafter appear, and for purposes of illustration of the invention, but not of limitation, an exemplary embodiment of the invention is shown in the appended drawing.
BRIEF DESCRIPTION OF THE DRAl~1ING
FIGURE 1 is an assembled perspective view of an over/under, dual chip in-line electronic circuit package of the present invention;
FIGURE 2 is a perspective view of the package assembly sho~vn in FIGURE I with the hermetic sealing lids removed;
FIGURE 3 is an exploded perspective view of the multiple chip 20 packagii~g assembly shown in FIGURE l;
FIGURE 4 is a bottom plan view of a vertically stacked array of substrate wafers which form a support core;
FIGURE 5 is a sectional view of the support core taken along the lines V-V of FIGURE 4;
FIGURE 6 is a partial sectional view which illustrates an example of device lead bonding, intra-level and inter-level conductive interconnect layout;FIGURE 7 is an exploded view of the wafer support core which - illustrates the various levels of conductive interconnect strips;
~IGURES 8 -12 are plan views of metalization deposits which form 30 the intra-level conductive strips and the inter-level conductive interconnects;
and, FIGURE 13 is a block diagram which identifies the function of each external pin of the package shown in FIGURE 1.
` ` ` ~ 1 6~65 DETAlLED DESCRIPTION 0~ Tl-l~ P~ ED E1~ 30DIMENTS
In the description wl~ich follows, the invention is described in combination with rundom access memory (R~M) circuit devices which are implemented by MOS/LSI techniques on semiconductor substrates. It will be appreciated, however, that the packaging assembly of the invention may be used 5 to encapsulate and interconnect discrete as well as integrated circuit devicesbut has particular utility for integrated circuits having multiple input/output leads. Accordingly, it should be understood that the invention may be incorporated in any modular structure housing two or more circuit devices~
Furthermore, the invention may be used to interconnect active or passive 10 substrate devices having a variety of circuit elements, including but not limited to discrete, micro-discrete and integrated circuit components, and hybrid combinations of discrete and integrated devices.
Like parts are marked throughout the specification and drawings with the same reference numerals, respectively. The drawing figures are not 15 necessarily to scale and in some instances portions have been exaggerated in order to more clearly depict certain features of the invention.
Referring now to the drawings, and in particular to ~IGURES 1, 2 and 3, a multilayer ceramic, multichip, over/under dual chip in-line packaging assembly 10 constructed according to the teachings of the invention is 20 illustrated. The package assembly 10 includes a composite core 12 which is intersected by four device cavities 14, 16, 18 and 20. The cavities are sealed by metal lids 22, 24 which are aligned with the top and bottom of the core and are sealed at both top and bottom by running the Issembly through a standard sealing form. The sealing procedure is carried out in an atmosphere of nitrogelI.
25 The lids are bonded to the top and bottom of the core at the interface of a solder preîorm 25 on the inside of each lid and conductive metalization deposits26, 28 along the top and bottom sealing surfaces of the core.
The core is punched, metalized and sintered to form a dense, multilayer ceramic core. A wide variety of ceramic raw materials may be used, 30 for example, alumina, zircon, aluminum silicates, titanium dioxide, or berylia ceramic. Exclusive of the lids 22, 24, the core 12 is formed by a vertically stacked array of six ceramic substrate wafers, beginning with an uppermost - wafer 30, intermediate wafers 32, 34, 36, 38, and a lowermost wafer 40. These ~ 1 65465 (~
ceramic layers are sintered to produce n monolitllic core struct~1rc. 1 he layers nre elongnted ceramic wafers having a length of approximately 1.1 inches in length, 0.29 inches in width, and 0.015 inch in thickness. The metalization deposits 26, 28 are preferably an alloy of tungsten, nickel and gold.
The packnge assembly 10 is an over/under, dual chip in-line 5 arrangement having twenty-two external connector pins 42 arral~ged in two parallel rows along the longitudinal edges of the package. The connector pin rows are laterally spaced along a 300 mil row center, according to industry standards. Additionally, adjacent pins 42 in each row are spaced relative to each other on 100 mil centers. The connector pins 42 preferably comprise a 10 forty-two percent nickel iron alloy. It will be appreciated that during assembly, the connector pins 42 are structurally interconnected by a connecting band ~not shown) integral with the pins, preferably stamped from the same metal sheet In most instances, the connecting bands remain attached to the connector pins for handling purposes only and are severed prior to ultimate use.
Prior to assembly, each ceramic wafer is punched to form cavities and vertical interconnect openings and is then metalized to form the hermetic sealing deposits 26, 28 and to form intra-level conductive strips and inter-level conductive interconnects for interconnecting circuit devices reccived within thecavities.
As can best be seen in FIGURES 2 and 3, identical RAM
semiconductor chips 44A, 44B, 44C and 44D are received within the device cavities. Each chip includes identical input/output leads 46 which are interconnected with each other and with the external connector pins 42 to permit the RAM memory chips to be operated on a multiplex basis. Although each chip includes sixteen input/output leads, all four RAM memory devices may be operated on a time sharing, multiple~ basis through only twenty-two external connector pins 42. According to this arrangement, a 2561~ RAM is implemented in the same package type as previously used for 161~ and 641~ 1~AM
memory packages, without changing package width. This is achieved by combining four 64}~ RAM chips 44A, 44B, 44C and 44D in the single package assembly lO. To remain within the established standard length constraints, two RAM chips, 44A and 44B were mounted in the top cavities and two RA~l chips 44C and 44D were mounted in the bottom cavities in an over/under, dual chip in-line configuration. This unique packaging approach permits four separate 3 memory devices to be mounted within a single standard package.
~ ~ 6S~65 In ordcr to mini~ c yickl loss duc to dc~cc~ivc I~M chiL)s, thc l~AM chips are con~plc~ely burned in, tcstcd nnd spccd matched before they are incorporated into the package assembly. The RAhl chips are preferably Mounted on a dielectric/conductor patterned tape assembly, and after testing are! scvered from the tape to producc input/output device leads 4G having a 5 predetermined length and array pattern compatible with automatic bonding.
The leads 46 are bonded to conductive bonding pads 48. Each conductive bonding pad 48 preferably comprises a composite conductive strip o tungsten applied by a silk screen printing process, followed by a plated deposit of nickel, with a plated gold overlay.
The multi-chip paclcage assembly 10 is a multiple cavity paclcage witll the top and next adjacent substrate layers 30, 32 having coincident windowopenings 50, 52, respectively, which in combination define the device cavity 14.Coincident window openings 54, 56 are likewise formed in the upper substrate wafers 30, 32 and in combination define the cavity 16. Coincident window openings 58, 60 and 62, 64 formed in the lower substrate wafers 38, 40 define the lower device cavities 18, 20, respectively.
Referring now to FIGURE 4, the window openings 58, 60 and 62, 64 which make up the device cavities 18, 20 are rectangular, concentric openings with the outermost openings 60, 64 being relatively larger than the coincident 20 interior window openings 58, 62, respectively. By this arrangement, annular device lead connecting surfaces 66, 68 are exposed around the border of the relatively smaller openings 58, 64, respectively. In this instance, the lead connecting surfaces 66, 68 each form a part of the under side of the substrate wafer 38 which overlies the lowermost bottom substrate wafer 40. Similar 25 annular lead connecting surfaces 70, 72 are exposed on the upper side of the uppermost intermediate substrate wafer 32.
~ eferring now to FIGURES 7 and 8 -12, intra-level conductive strips 74 extend across the surfaces of the intermediate wafer substrates 32, 34, 36 and 38. The intra-level conductive strips 74 are deposited in an intricate 30 pattern as can best be seen in FIGURES 8 -12. According to a predetermined interconnection plan, selected ones of the intra-level conductive strips 74 extend from the bonding pads 48 along the interface of adjacent substrate wafers to the edge of the wafer on which they are deposited for connection to an external connector pin 42. Certain ones of the intra-level conductive strips, - ` ` i 1 6S~65 designnted as strips 76, exte1ld from bonding pads across the surface of the substrate wafer and terminate at a conductive inter-leYel intercomlect 78 for connection to an intra-level conductive strip 74 on the surface of an underlyingsubstrate wafer.
The intra-level conductive strips 74 preferably comprise tungsten 5 and are silk screen printed onto the wafer surface according to conventional printing techniques. According to this interconnection arrangement, corresponding pins of each R~M chip 44A, 44B, 44C and 4~D; which are functionally equivalçllt, are interconnected to each other, and to a common external connector pin 42. For example, device lead No. 2 of each RAM chip, which is the DATA INPUT terminal, is interconnected with all other DATA
INPU T terminals No. 2 by means of intra-level conductor strips 74, 76 and inter-level conductive interconnects 78 which are deposited on or embedded in the intermediate substrate wafers 32, 34, 36 and 38.
- This interconnection of multiple devices is made possible by the provision of the intermediate substrate wafer 34, botll sides of which have intra-level conductive strips 74, 76. The wafer 34 is intersected by inter-levelconnective interconnects 78 which connect intra-level strips of t~vo different levels Thus the intermediate substrate wafer 34 serves not only to interconnect both of the RAM chips in the upper in-line cavities 14, 16, but simultaneously interconnects the RAM chips 4-lC, 44D in the lower in-line cavities 18, 20, and further simultaneously conl~ ~Ls predetermined ones of the device terminals having a common function to a common external connector pin 42. Thus the provision of the intermediate substrate wafer having intra-level conductive strips on both sides as well as inter-level conductive interconnects makes possible both horizontal and vertical interconnection of aU circuit devices and external connector pins.
Additionally, internal circuit connections between the devices, such as common ground connections, are provided by conductive ground strips 80, 82 and 84, 86. Referring to FIGURES 6, 8 and 12, each RAM chip includes an internal ground terminal, designated "G", and a package grounding pad 88 which is directly bonded to the underlying ground strip. The ground strips are all interconnected by vertically aligned inter-level conductive interconnects 90 which are embedded in a central location in each substrate wafer.
The intermediate substrate wafers 34, 36 simultaneously provide a ~ ............... . ... . . . . . . .... .... _ ~ 1 6S465 structural moullting bllse for eacll chip, while insulating the top and bottom chips witll respect to each other. The provision of these two intermediate substrate wafers also makes possible tlle printing of the conductive intra-levelstrips on the top and under sides of wafer 34, which is the key to the horizontal and vertical interconnection wllich ties in the common input/output termin~ls ofall four Rt~M cllipS.
It should be noted that the row address strobe ~AS and column address strobe CAS terminals of each device are maintained separate with respect to each other, each being connected to a separate external connector pin. This allows each RAM cllip to be selected and used on a time sharing, multiplex bflsis. Therefore only twenty-two pins are needed to operate four RAM chips, each having sixteen input/output terminals.
The multiple intra-level conductive strip arrangement, in combination with the inter-level conductive interconnects, provides pattern flexibility for arranging the bond pads for attachment to the device input/output leads. Additionally, the device substrate area is not compromised, nor is the hermetic seal surface area reduced by this arrangement.
Consequently, the bonding pads need not be offset or staggered with respect to each other, thereby making possible the simultaneous, direct bonding of the device input/output leads to the bonding pads in an automatic bonding operation. Thus the device density of the package is substantially increased from two devices to four devices, without compromising device substrate area or sealing surface requirements, and also conforming with packaging dimensions established by industry standards.
While a particular embodiment of the invention has been illustrated and described in detail, it will be apparent that various modifications can be made without departing from the spirit and scope of the invelltion.
What is claimed is:
_ . . ... _ . _
BAC~GROUND OF THE INVENTlON
Field of the Invention:
The present invention relates generally to electronic packaging, and particularly to inter-layer and intra-layer connecting means for multi-chip modules.
5 Description of the Prior Art:
The packaging of electronic equipment has become a major factor in the design and manufacture of contemporary electronic systems. New packaging techniques are required to meet the demand for reduced physical size and improved reliability at lower cost. The problem of efficient packaging is 10 particularly important ir~ electronic circuits which utilize microcircuit structures of the type implemented by LSI techniques on a semiconductor substrate chip.
Conventional electronic circuit packages for semiconductor chips are adapted to enclose and hermetically seal the chip devices, while also 15 providing heat dissipation, structural support, electrical attachment of device leads to external pin connectors, and electrical interconnection with other devices in the package. Such packages are usually formed of one or more layers of a non-conductive substrate waf er, with a central cavity in which the semiconductor chip is received. Flexible metal leads are extended between the 20 layers to the central cavity for connection with the device input/output leads.
Because of industry standards relating to the exterior dimensions for electroniccircuit packages, including spacing between leads and between lead rows in the "~
" _ _ ,~
__,. __ , ~ . . __ . _ .. . . . . .
` ` ` ` I J 65465 case of the standard dual in-line package, the presence of multiple flexible metal leads has limited the number of circuit devices which can be encapsulated in a standard package.
There is a continuing interest in increasing the device packaging density, particularly for semiconductor memory circuitry used in high speed 5 data processing circuits, for example random access memory (RAM) circuits implemented by MOS/LSI techniques on semiconductor substrate.chips. One particular industry package standard for memory devices specifies 300 mil row spacing with external pins mounted on 100 mil cènters in each row. I~lemory capacity for this standard package can be upgraded from a pair of 81~ bit R~M
10 devicesJ to a pair of 16K bit RAM devices, or to a pair of 64K bit RAM devices.
As the memory capacity of the chips becomes largerJ the chip substrate area required to implement the increased memory is also increased, thereby reducing to a minimum the area available for the device lead attachment within a package having standard dimensions. Accordingly, various 15 attempts have been made to redesign the package in order to provide a larger chip cavity. It will be appreciated that the mounting area available for the device substrate, for a given standard package, is necessarily limited by the space required for device lead bonding and by the minimum dimensions necessary to provide a hermetic seal. The conventional dual chip, in-line 20 packaging assembly has~resulted because of the memory substrate area constraint and has doubled memory capacity while conforming with lead row standards. Although memory capacity may be increased by adding additional memory chips in tandem, in-line relation with the standard dual chip in-line configuration, because of established standards for lead center spacing and 25 maximum number of external pins and package length, such arrangements have not achieved widespread acceptance. Therefore there is a serious and continuing need for an improved electronic circuit package in which the device density can be s~bstantially increased while conforming with established industry packaging standards.
SUMMARY OF OBJECTS OF THE INVENTION
Accordingly, the principal object of the present invention is to _ ~ 1 654~5 provide an clectronic circuit paclcage having n substantiaUy increnscd device packagillg density which conforms with established standards.
A rel~ted object is to provide an electronic circuit package for encapsulating and interconnecting multiple semiconductor chips.
Another object of the invelltion is to provide an electronic circuit S package for encapsulating and interconnecting four identical semiconductor chips for multiplex operation.
Yet another object of the invention is to provide a~ electronic circuit package for encapsulating and interconnecti;Ig mlùtiple pairs of semiconductor circuit devices in an over/under, dual chip in-line arrangement in10 which each chip device may be operated independently of the other chip devices on a multiplex basis with only a minimum number of external connector pins.
SVMMARY OF THE INVENTION
The foregoing objects are realized by a vertically stacked array of 15 substrate wafers which form a support core in which windows are formed for separately receiving an~ mounting semiconductor chip circuit devices. Device support surfaces and device lead connecting surfaces are exposed by each window on one or more of the substrate wafers. Intra-level conductive strips are separately disposed on each lead connecting surface for attachment to the 20 input/output leads of each semiconductor chip and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins Inte~level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra-level conductive strips of a different level.
In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement. In this arrangement, two RAM chips are mounted n~ in^
line relation on a common substrate wafer at an upper level, and two RAM chips are mounted on a common substrate wafer at a lower level. Corresponding data and power terminals of the chips on the upper level are interconnected in common with each other and to a common external pin by the combination of intra-level conductive strips extending through the interface of adjacent wafer substrates at first and second levels, and by inter-level conductive 65~65 intercomlects which intersect nnd nre clllbeddc~ in the substr-ltc wnl`er on whicll the de~icc leads nre bondcd. Idellticnl powcr alld data tcrmill~ùs o~ th~ lower R~M cllips are similarly intercomlected with each other and are interconnected with the correspondil-g data nnd power terminals of the upper R~l cllipS by an intermediate group of intrfl-level conductive strips and by inte~level 5 conductive interconnects which intersect the substrate wafers which form the interface along which the intermediate group of intra-level conductive strips are disposed.
The novel features which chnracterize the invention are defined by the appended claims The foregoin~ and other objects, advantnges and fefltures 10 of the invention will hereinafter appear, and for purposes of illustration of the invention, but not of limitation, an exemplary embodiment of the invention is shown in the appended drawing.
BRIEF DESCRIPTION OF THE DRAl~1ING
FIGURE 1 is an assembled perspective view of an over/under, dual chip in-line electronic circuit package of the present invention;
FIGURE 2 is a perspective view of the package assembly sho~vn in FIGURE I with the hermetic sealing lids removed;
FIGURE 3 is an exploded perspective view of the multiple chip 20 packagii~g assembly shown in FIGURE l;
FIGURE 4 is a bottom plan view of a vertically stacked array of substrate wafers which form a support core;
FIGURE 5 is a sectional view of the support core taken along the lines V-V of FIGURE 4;
FIGURE 6 is a partial sectional view which illustrates an example of device lead bonding, intra-level and inter-level conductive interconnect layout;FIGURE 7 is an exploded view of the wafer support core which - illustrates the various levels of conductive interconnect strips;
~IGURES 8 -12 are plan views of metalization deposits which form 30 the intra-level conductive strips and the inter-level conductive interconnects;
and, FIGURE 13 is a block diagram which identifies the function of each external pin of the package shown in FIGURE 1.
` ` ` ~ 1 6~65 DETAlLED DESCRIPTION 0~ Tl-l~ P~ ED E1~ 30DIMENTS
In the description wl~ich follows, the invention is described in combination with rundom access memory (R~M) circuit devices which are implemented by MOS/LSI techniques on semiconductor substrates. It will be appreciated, however, that the packaging assembly of the invention may be used 5 to encapsulate and interconnect discrete as well as integrated circuit devicesbut has particular utility for integrated circuits having multiple input/output leads. Accordingly, it should be understood that the invention may be incorporated in any modular structure housing two or more circuit devices~
Furthermore, the invention may be used to interconnect active or passive 10 substrate devices having a variety of circuit elements, including but not limited to discrete, micro-discrete and integrated circuit components, and hybrid combinations of discrete and integrated devices.
Like parts are marked throughout the specification and drawings with the same reference numerals, respectively. The drawing figures are not 15 necessarily to scale and in some instances portions have been exaggerated in order to more clearly depict certain features of the invention.
Referring now to the drawings, and in particular to ~IGURES 1, 2 and 3, a multilayer ceramic, multichip, over/under dual chip in-line packaging assembly 10 constructed according to the teachings of the invention is 20 illustrated. The package assembly 10 includes a composite core 12 which is intersected by four device cavities 14, 16, 18 and 20. The cavities are sealed by metal lids 22, 24 which are aligned with the top and bottom of the core and are sealed at both top and bottom by running the Issembly through a standard sealing form. The sealing procedure is carried out in an atmosphere of nitrogelI.
25 The lids are bonded to the top and bottom of the core at the interface of a solder preîorm 25 on the inside of each lid and conductive metalization deposits26, 28 along the top and bottom sealing surfaces of the core.
The core is punched, metalized and sintered to form a dense, multilayer ceramic core. A wide variety of ceramic raw materials may be used, 30 for example, alumina, zircon, aluminum silicates, titanium dioxide, or berylia ceramic. Exclusive of the lids 22, 24, the core 12 is formed by a vertically stacked array of six ceramic substrate wafers, beginning with an uppermost - wafer 30, intermediate wafers 32, 34, 36, 38, and a lowermost wafer 40. These ~ 1 65465 (~
ceramic layers are sintered to produce n monolitllic core struct~1rc. 1 he layers nre elongnted ceramic wafers having a length of approximately 1.1 inches in length, 0.29 inches in width, and 0.015 inch in thickness. The metalization deposits 26, 28 are preferably an alloy of tungsten, nickel and gold.
The packnge assembly 10 is an over/under, dual chip in-line 5 arrangement having twenty-two external connector pins 42 arral~ged in two parallel rows along the longitudinal edges of the package. The connector pin rows are laterally spaced along a 300 mil row center, according to industry standards. Additionally, adjacent pins 42 in each row are spaced relative to each other on 100 mil centers. The connector pins 42 preferably comprise a 10 forty-two percent nickel iron alloy. It will be appreciated that during assembly, the connector pins 42 are structurally interconnected by a connecting band ~not shown) integral with the pins, preferably stamped from the same metal sheet In most instances, the connecting bands remain attached to the connector pins for handling purposes only and are severed prior to ultimate use.
Prior to assembly, each ceramic wafer is punched to form cavities and vertical interconnect openings and is then metalized to form the hermetic sealing deposits 26, 28 and to form intra-level conductive strips and inter-level conductive interconnects for interconnecting circuit devices reccived within thecavities.
As can best be seen in FIGURES 2 and 3, identical RAM
semiconductor chips 44A, 44B, 44C and 44D are received within the device cavities. Each chip includes identical input/output leads 46 which are interconnected with each other and with the external connector pins 42 to permit the RAM memory chips to be operated on a multiplex basis. Although each chip includes sixteen input/output leads, all four RAM memory devices may be operated on a time sharing, multiple~ basis through only twenty-two external connector pins 42. According to this arrangement, a 2561~ RAM is implemented in the same package type as previously used for 161~ and 641~ 1~AM
memory packages, without changing package width. This is achieved by combining four 64}~ RAM chips 44A, 44B, 44C and 44D in the single package assembly lO. To remain within the established standard length constraints, two RAM chips, 44A and 44B were mounted in the top cavities and two RA~l chips 44C and 44D were mounted in the bottom cavities in an over/under, dual chip in-line configuration. This unique packaging approach permits four separate 3 memory devices to be mounted within a single standard package.
~ ~ 6S~65 In ordcr to mini~ c yickl loss duc to dc~cc~ivc I~M chiL)s, thc l~AM chips are con~plc~ely burned in, tcstcd nnd spccd matched before they are incorporated into the package assembly. The RAhl chips are preferably Mounted on a dielectric/conductor patterned tape assembly, and after testing are! scvered from the tape to producc input/output device leads 4G having a 5 predetermined length and array pattern compatible with automatic bonding.
The leads 46 are bonded to conductive bonding pads 48. Each conductive bonding pad 48 preferably comprises a composite conductive strip o tungsten applied by a silk screen printing process, followed by a plated deposit of nickel, with a plated gold overlay.
The multi-chip paclcage assembly 10 is a multiple cavity paclcage witll the top and next adjacent substrate layers 30, 32 having coincident windowopenings 50, 52, respectively, which in combination define the device cavity 14.Coincident window openings 54, 56 are likewise formed in the upper substrate wafers 30, 32 and in combination define the cavity 16. Coincident window openings 58, 60 and 62, 64 formed in the lower substrate wafers 38, 40 define the lower device cavities 18, 20, respectively.
Referring now to FIGURE 4, the window openings 58, 60 and 62, 64 which make up the device cavities 18, 20 are rectangular, concentric openings with the outermost openings 60, 64 being relatively larger than the coincident 20 interior window openings 58, 62, respectively. By this arrangement, annular device lead connecting surfaces 66, 68 are exposed around the border of the relatively smaller openings 58, 64, respectively. In this instance, the lead connecting surfaces 66, 68 each form a part of the under side of the substrate wafer 38 which overlies the lowermost bottom substrate wafer 40. Similar 25 annular lead connecting surfaces 70, 72 are exposed on the upper side of the uppermost intermediate substrate wafer 32.
~ eferring now to FIGURES 7 and 8 -12, intra-level conductive strips 74 extend across the surfaces of the intermediate wafer substrates 32, 34, 36 and 38. The intra-level conductive strips 74 are deposited in an intricate 30 pattern as can best be seen in FIGURES 8 -12. According to a predetermined interconnection plan, selected ones of the intra-level conductive strips 74 extend from the bonding pads 48 along the interface of adjacent substrate wafers to the edge of the wafer on which they are deposited for connection to an external connector pin 42. Certain ones of the intra-level conductive strips, - ` ` i 1 6S~65 designnted as strips 76, exte1ld from bonding pads across the surface of the substrate wafer and terminate at a conductive inter-leYel intercomlect 78 for connection to an intra-level conductive strip 74 on the surface of an underlyingsubstrate wafer.
The intra-level conductive strips 74 preferably comprise tungsten 5 and are silk screen printed onto the wafer surface according to conventional printing techniques. According to this interconnection arrangement, corresponding pins of each R~M chip 44A, 44B, 44C and 4~D; which are functionally equivalçllt, are interconnected to each other, and to a common external connector pin 42. For example, device lead No. 2 of each RAM chip, which is the DATA INPUT terminal, is interconnected with all other DATA
INPU T terminals No. 2 by means of intra-level conductor strips 74, 76 and inter-level conductive interconnects 78 which are deposited on or embedded in the intermediate substrate wafers 32, 34, 36 and 38.
- This interconnection of multiple devices is made possible by the provision of the intermediate substrate wafer 34, botll sides of which have intra-level conductive strips 74, 76. The wafer 34 is intersected by inter-levelconnective interconnects 78 which connect intra-level strips of t~vo different levels Thus the intermediate substrate wafer 34 serves not only to interconnect both of the RAM chips in the upper in-line cavities 14, 16, but simultaneously interconnects the RAM chips 4-lC, 44D in the lower in-line cavities 18, 20, and further simultaneously conl~ ~Ls predetermined ones of the device terminals having a common function to a common external connector pin 42. Thus the provision of the intermediate substrate wafer having intra-level conductive strips on both sides as well as inter-level conductive interconnects makes possible both horizontal and vertical interconnection of aU circuit devices and external connector pins.
Additionally, internal circuit connections between the devices, such as common ground connections, are provided by conductive ground strips 80, 82 and 84, 86. Referring to FIGURES 6, 8 and 12, each RAM chip includes an internal ground terminal, designated "G", and a package grounding pad 88 which is directly bonded to the underlying ground strip. The ground strips are all interconnected by vertically aligned inter-level conductive interconnects 90 which are embedded in a central location in each substrate wafer.
The intermediate substrate wafers 34, 36 simultaneously provide a ~ ............... . ... . . . . . . .... .... _ ~ 1 6S465 structural moullting bllse for eacll chip, while insulating the top and bottom chips witll respect to each other. The provision of these two intermediate substrate wafers also makes possible tlle printing of the conductive intra-levelstrips on the top and under sides of wafer 34, which is the key to the horizontal and vertical interconnection wllich ties in the common input/output termin~ls ofall four Rt~M cllipS.
It should be noted that the row address strobe ~AS and column address strobe CAS terminals of each device are maintained separate with respect to each other, each being connected to a separate external connector pin. This allows each RAM cllip to be selected and used on a time sharing, multiplex bflsis. Therefore only twenty-two pins are needed to operate four RAM chips, each having sixteen input/output terminals.
The multiple intra-level conductive strip arrangement, in combination with the inter-level conductive interconnects, provides pattern flexibility for arranging the bond pads for attachment to the device input/output leads. Additionally, the device substrate area is not compromised, nor is the hermetic seal surface area reduced by this arrangement.
Consequently, the bonding pads need not be offset or staggered with respect to each other, thereby making possible the simultaneous, direct bonding of the device input/output leads to the bonding pads in an automatic bonding operation. Thus the device density of the package is substantially increased from two devices to four devices, without compromising device substrate area or sealing surface requirements, and also conforming with packaging dimensions established by industry standards.
While a particular embodiment of the invention has been illustrated and described in detail, it will be apparent that various modifications can be made without departing from the spirit and scope of the invelltion.
What is claimed is:
_ . . ... _ . _
Claims (10)
1. An electronic circuit package for encapsulating circuit devices each having input/output leads, said package including a vertically stacked array of substrate wafers defining a support core, said support core having cavities intersecting one or more of said substrate wafers for separately receiving the circuit devices; device support surfaces and device lead connecting surfaces being exposed on one or more of said substrate wafers;
intra-level conductive strips separately disposed on each lead connecting surface for attachment to the input/output leads of one of the circuit devices;
intra-level conductive strips of each group extending along the interface of oneor more superposed pairs of substrate wafers for connection to external connector pins; and, inter-level conductive means embedded in one or more of said substrates interconnecting the intra-level conductive strips of one level with the intra-level conductive strips of a different level
intra-level conductive strips separately disposed on each lead connecting surface for attachment to the input/output leads of one of the circuit devices;
intra-level conductive strips of each group extending along the interface of oneor more superposed pairs of substrate wafers for connection to external connector pins; and, inter-level conductive means embedded in one or more of said substrates interconnecting the intra-level conductive strips of one level with the intra-level conductive strips of a different level
2. The electronic circuit package as defined in Claim 1, said support core including at least one intermediate wafer having intra-level conductive strips deposited over both of its interior sides, and at least one inter-level conductive interconnect embedded in the intermediate wafer interconnecting an intra-level strip on one side with an intra-level strip on the reverse side of the intermediate wafer.
3. The electronic circuit package as defined in Claim 1, said support core having at least two device cavities vertically disposed relative toeach other within said array, and at least one intermediate substrate wafer interposed between the device cavities.
4. The electronic circuit package as defined in Claim 1, said support core comprising six rectangular wafers including an uppermost wafer pair, a lowermost wafer pair, and an intermediate wafer pair confined between the upper and lower wafer pairs, the wafers of the uppermost and lowermost pairs each having coincident window openings defining the device cavities.
5. An electronic circuit package for encapsulating first and second circuit devices each having input/output leads, said package including a vertically stacked array of substrate wafers, said stacked array comprising:
an upper wafer having a window opening;
a lower wafer having a window opening;
intermediate wafer means interleaved between the upper and lower wafers, said intermediate wafer means having upper and lower side surfaces coincident with the upper and lower window openings, respectively, the upper and lower side surfaces each having device support surfaces and device lead connecting surfaces accessible through the window openings, respectively;
first and second groups of intra-level conductive strips disposed on the upper and lower device lead connecting surfaces, respectively, for attachment to the input/output leads of the first and second circuit devices, respectively, conductive strips of each group extending at least partially across the upper and lower side surfaces of the intermediate wafer means along the interface of the interleaved wafers to a peripheral edge of the intermediate wafer means for connection to external connector pins.
an upper wafer having a window opening;
a lower wafer having a window opening;
intermediate wafer means interleaved between the upper and lower wafers, said intermediate wafer means having upper and lower side surfaces coincident with the upper and lower window openings, respectively, the upper and lower side surfaces each having device support surfaces and device lead connecting surfaces accessible through the window openings, respectively;
first and second groups of intra-level conductive strips disposed on the upper and lower device lead connecting surfaces, respectively, for attachment to the input/output leads of the first and second circuit devices, respectively, conductive strips of each group extending at least partially across the upper and lower side surfaces of the intermediate wafer means along the interface of the interleaved wafers to a peripheral edge of the intermediate wafer means for connection to external connector pins.
6. The electronic circuit package as defined in Claim 5, including inter-level conductive means embedded in said intermediate wafer means interconnecting an intra-level conductive strip of the upper group to an intra-level conductive strip of the lower group.
7. An electronic circuit package for encapsulating first and second circuit devices each having input/output leads, said package including a vertically stacked array of substrate wafers, said stacked array comprising:
an upper wafer having first and second window openings spaced in in-line relation;
a lower wafer having an interior side surface underlying the first and second window openings, the side surfaces of said lower wafer coincident With the first and second window openings each having device support areas and device lead support surfaces accessible through the window openings, respectively; and, 12 first and second groups of conductive strips disposed on the first and second device lead connecting surfaces, respectively, for attachment to the input/output lends of the first and second circuit devices, respectively, conductive strips of each group extending at least partially across the interiorsurface of the lower wafer along the interface of the upper and lower wafers to a peripheral edge of the lower wafer for connection to external connector pins.
an upper wafer having first and second window openings spaced in in-line relation;
a lower wafer having an interior side surface underlying the first and second window openings, the side surfaces of said lower wafer coincident With the first and second window openings each having device support areas and device lead support surfaces accessible through the window openings, respectively; and, 12 first and second groups of conductive strips disposed on the first and second device lead connecting surfaces, respectively, for attachment to the input/output lends of the first and second circuit devices, respectively, conductive strips of each group extending at least partially across the interiorsurface of the lower wafer along the interface of the upper and lower wafers to a peripheral edge of the lower wafer for connection to external connector pins.
8. An electronic circuit package for encapsulating first and second circuit devices each having input/output leads, said package including a vertically stacked array of substrate wafers, said stacked array comprising:
an uppermost pair of superposed wafers each having mutually overlapping surfaces and coincident window openings;
a lowermost pair of superposed wafers each having mutually overlapping surfaces and coincident window openings;
the coincident window openings of each wafer pair defining upper and lower cavities, respectively, for receiving the first and second circuit devices, respectively, the window opening of the outermost wafer of each pair being at least partially offset with respect to the inner window opening of eachwafer cavity thereby exposing at least a portion of the wafer surface surrounding the inner window opening and defining upper and lower device lead connecting surfaces, respectively;
intermediate wafer means confined between the upper and lower wafer pairs providing a support base for said circuit devices;
first and second groups of conductive strips disposed on the upper and lower device lead connecting surfaces, respectively, for attachment to the input/output leads of the first and second circuit devices, respectively, and extending at least partially across the wafer in which the inner window is formed along the interface of the overlapping wafer surfaces to a peripheral edge of the inner wafer of each wafer pair, respectively, for connection to an external conductor pin.
an uppermost pair of superposed wafers each having mutually overlapping surfaces and coincident window openings;
a lowermost pair of superposed wafers each having mutually overlapping surfaces and coincident window openings;
the coincident window openings of each wafer pair defining upper and lower cavities, respectively, for receiving the first and second circuit devices, respectively, the window opening of the outermost wafer of each pair being at least partially offset with respect to the inner window opening of eachwafer cavity thereby exposing at least a portion of the wafer surface surrounding the inner window opening and defining upper and lower device lead connecting surfaces, respectively;
intermediate wafer means confined between the upper and lower wafer pairs providing a support base for said circuit devices;
first and second groups of conductive strips disposed on the upper and lower device lead connecting surfaces, respectively, for attachment to the input/output leads of the first and second circuit devices, respectively, and extending at least partially across the wafer in which the inner window is formed along the interface of the overlapping wafer surfaces to a peripheral edge of the inner wafer of each wafer pair, respectively, for connection to an external conductor pin.
9. The electronoic circuit package as defined in Claim 8, the intermediate wafer means comprising first and second superposed wafers, one of said intermediate wafers including intra-level conductive strips on both of its sides, and the other intermediate wafer including intra-level conductive strips only on a single side facing one of the cavities, and including at least one inter-level conductive interconnect embedded in each intermediate wafer and interconnecting intra-level strips of one level with intra-level strips of a different level.
10. An over/under, dual in-line multiple chip module comprising, in combination:
a vertically stacked array of substrate wafers defining a support core, said support core including first and second intermediate wafers confined between uppermost and lowermost wafers, said core having first and second cavities intersecting one or more of said wafers along an upper level and third and fourth cavities intersecting one or more of said wafers along a lower level wherein device support and lead connecting surfaces are exposed on said intermediate wafers;
bonding pads deposited onto the lead connecting surfaces in each cavity;
a semiconductor chip device having input/output leads received in each cavity, each chip device being mounted on the support surface and the input/output leads of each device being joined to the bonding pads in each cavity;
external connector pins attached in first and second parallel rows along opposite sides of said array;
intra-level conductive strips separately disposed on each lead connecting surface having one end electrically coupled to one of said bonding pads and the opposite end electrically coupled to one of the external connector pins, one of said intermediate wafers having intra-level conductive strips deposited over both of its interior sides, and the other intermediate wafer having intra-level conductive strips only on a single side facing one of said cavity pairs;
at least one inter-level conductive interconncect embedded in each wafer having intra-level conductive strips electrically interconnecting intra-level conductive strips of one level with intra-level conductive strips of different level, whereby functionally equivalent terminals of all four chips are interconnected in common with each other and to a common external connector pin thereby permitting the devices to be operated on a time-sharing, multiplex basis through a minimum number of external connector pins.
a vertically stacked array of substrate wafers defining a support core, said support core including first and second intermediate wafers confined between uppermost and lowermost wafers, said core having first and second cavities intersecting one or more of said wafers along an upper level and third and fourth cavities intersecting one or more of said wafers along a lower level wherein device support and lead connecting surfaces are exposed on said intermediate wafers;
bonding pads deposited onto the lead connecting surfaces in each cavity;
a semiconductor chip device having input/output leads received in each cavity, each chip device being mounted on the support surface and the input/output leads of each device being joined to the bonding pads in each cavity;
external connector pins attached in first and second parallel rows along opposite sides of said array;
intra-level conductive strips separately disposed on each lead connecting surface having one end electrically coupled to one of said bonding pads and the opposite end electrically coupled to one of the external connector pins, one of said intermediate wafers having intra-level conductive strips deposited over both of its interior sides, and the other intermediate wafer having intra-level conductive strips only on a single side facing one of said cavity pairs;
at least one inter-level conductive interconncect embedded in each wafer having intra-level conductive strips electrically interconnecting intra-level conductive strips of one level with intra-level conductive strips of different level, whereby functionally equivalent terminals of all four chips are interconnected in common with each other and to a common external connector pin thereby permitting the devices to be operated on a time-sharing, multiplex basis through a minimum number of external connector pins.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12091780A | 1980-02-12 | 1980-02-12 | |
| US120,917 | 1980-02-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1165465A true CA1165465A (en) | 1984-04-10 |
Family
ID=22393267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000370651A Expired CA1165465A (en) | 1980-02-12 | 1981-02-11 | Over/under dual in-line chip package |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS6356706B2 (en) |
| CA (1) | CA1165465A (en) |
| FR (1) | FR2476389A1 (en) |
| GB (1) | GB2083285B (en) |
| NL (1) | NL8020334A (en) |
| WO (1) | WO1981002367A1 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58159360A (en) * | 1982-03-17 | 1983-09-21 | Fujitsu Ltd | Semiconductor device |
| US4727410A (en) * | 1983-11-23 | 1988-02-23 | Cabot Technical Ceramics, Inc. | High density integrated circuit package |
| AU568416B2 (en) * | 1983-12-28 | 1987-12-24 | Raytheon Company | Flat package for integrated circuit memory chips |
| US4598308A (en) * | 1984-04-02 | 1986-07-01 | Burroughs Corporation | Easily repairable, low cost, high speed electromechanical assembly of integrated circuit die |
| US4630096A (en) * | 1984-05-30 | 1986-12-16 | Motorola, Inc. | High density IC module assembly |
| US4734315A (en) * | 1985-06-05 | 1988-03-29 | Joyce Florence Space-Bate | Low power circuitry components |
| EP0241236A3 (en) * | 1986-04-11 | 1989-03-08 | AT&T Corp. | Cavity package for saw devices and associated electronics |
| GB2199182A (en) * | 1986-12-18 | 1988-06-29 | Marconi Electronic Devices | Multilayer circuit arrangement |
| FR2625042B1 (en) * | 1987-12-22 | 1990-04-20 | Thomson Csf | MODULAR HYBRID MICROELECTRONIC STRUCTURE WITH HIGH INTEGRATION DENSITY |
| US5150196A (en) * | 1989-07-17 | 1992-09-22 | Hughes Aircraft Company | Hermetic sealing of wafer scale integrated wafer |
| FR2772516B1 (en) * | 1997-12-12 | 2003-07-04 | Ela Medical Sa | ELECTRONIC CIRCUIT, IN PARTICULAR FOR AN ACTIVE IMPLANTABLE MEDICAL DEVICE SUCH AS A CARDIAC STIMULATOR OR DEFIBRILLATOR, AND ITS MANUFACTURING METHOD |
| GB9915076D0 (en) * | 1999-06-28 | 1999-08-25 | Shen Ming Tung | Integrated circuit packaging structure |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3341649A (en) * | 1964-01-17 | 1967-09-12 | Signetics Corp | Modular package for semiconductor devices |
| US3372310A (en) * | 1965-04-30 | 1968-03-05 | Radiation Inc | Universal modular packages for integrated circuits |
| US3500440A (en) * | 1968-01-08 | 1970-03-10 | Interamericano Projects Inc | Functional building blocks facilitating mass production of electronic equipment by unskilled labor |
| US3555364A (en) * | 1968-01-31 | 1971-01-12 | Drexel Inst Of Technology | Microelectronic modules and assemblies |
| JPS5332233B1 (en) * | 1968-12-25 | 1978-09-07 | ||
| US3746934A (en) * | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
| US3760090A (en) * | 1971-08-19 | 1973-09-18 | Globe Union Inc | Electronic circuit package and method for making same |
| US3927815A (en) * | 1971-11-22 | 1975-12-23 | Ngk Insulators Ltd | Method for producing multilayer metallized beryllia ceramics |
| US3777220A (en) * | 1972-06-30 | 1973-12-04 | Ibm | Circuit panel and method of construction |
| US3777221A (en) * | 1972-12-18 | 1973-12-04 | Ibm | Multi-layer circuit package |
| US4012766A (en) * | 1973-08-28 | 1977-03-15 | Western Digital Corporation | Semiconductor package and method of manufacture thereof |
| US4038488A (en) * | 1975-05-12 | 1977-07-26 | Cambridge Memories, Inc. | Multilayer ceramic multi-chip, dual in-line packaging assembly |
| US4079511A (en) * | 1976-07-30 | 1978-03-21 | Amp Incorporated | Method for packaging hermetically sealed integrated circuit chips on lead frames |
| US4224637A (en) * | 1978-08-10 | 1980-09-23 | Minnesota Mining And Manufacturing Company | Leaded mounting and connector unit for an electronic device |
-
1980
- 1980-05-22 JP JP55502028A patent/JPS6356706B2/ja not_active Expired
- 1980-05-22 WO PCT/US1980/000662 patent/WO1981002367A1/en not_active Ceased
- 1980-05-22 GB GB8129603A patent/GB2083285B/en not_active Expired
- 1980-05-22 NL NL8020334A patent/NL8020334A/nl unknown
-
1981
- 1981-02-11 CA CA000370651A patent/CA1165465A/en not_active Expired
- 1981-02-12 FR FR8102748A patent/FR2476389A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2476389A1 (en) | 1981-08-21 |
| JPS6356706B2 (en) | 1988-11-09 |
| GB2083285A (en) | 1982-03-17 |
| NL8020334A (en) | 1982-01-04 |
| WO1981002367A1 (en) | 1981-08-20 |
| JPS57500220A (en) | 1982-02-04 |
| GB2083285B (en) | 1984-08-15 |
| FR2476389B1 (en) | 1983-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4972253A (en) | Programmable ceramic high performance custom package | |
| US5744862A (en) | Reduced thickness semiconductor device with IC packages mounted in openings on substrate | |
| US5600541A (en) | Vertical IC chip stack with discrete chip carriers formed from dielectric tape | |
| US5484959A (en) | High density lead-on-package fabrication method and apparatus | |
| US4763188A (en) | Packaging system for multiple semiconductor devices | |
| US5283717A (en) | Circuit assembly having interposer lead frame | |
| US5455385A (en) | Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses | |
| US5016138A (en) | Three dimensional integrated circuit package | |
| US4953060A (en) | Stackable integrated circuit chip package with improved heat removal | |
| US5475264A (en) | Arrangement having multilevel wiring structure used for electronic component module | |
| US4288841A (en) | Double cavity semiconductor chip carrier | |
| US5943213A (en) | Three-dimensional electronic module | |
| US4038488A (en) | Multilayer ceramic multi-chip, dual in-line packaging assembly | |
| US4783697A (en) | Leadless chip carrier for RF power transistors or the like | |
| US5780925A (en) | Lead frame package for electronic devices | |
| US5701233A (en) | Stackable modules and multimodular assemblies | |
| US4730232A (en) | High density microelectronic packaging module for high speed chips | |
| US6331939B1 (en) | Stackable ball grid array package | |
| US5448511A (en) | Memory stack with an integrated interconnect and mounting structure | |
| US5563446A (en) | Surface mount peripheral leaded and ball grid array package | |
| US4887148A (en) | Pin grid array package structure | |
| JPS61101067A (en) | Memory module | |
| CA1165465A (en) | Over/under dual in-line chip package | |
| JPH05251630A (en) | Semiconductor device | |
| CN100550377C (en) | A single package containing multiple integrated circuit devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |