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NZ509450A - Input/output interface and device abstraction - Google Patents

Input/output interface and device abstraction

Info

Publication number
NZ509450A
NZ509450A NZ509450A NZ50945099A NZ509450A NZ 509450 A NZ509450 A NZ 509450A NZ 509450 A NZ509450 A NZ 509450A NZ 50945099 A NZ50945099 A NZ 50945099A NZ 509450 A NZ509450 A NZ 509450A
Authority
NZ
New Zealand
Prior art keywords
iocb
virtual device
game
message
cpu
Prior art date
Application number
NZ509450A
Inventor
Anthony Wayne Bond
Ronald Edward Mach
Original Assignee
Aristocrat Technologies Au
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aristocrat Technologies Au filed Critical Aristocrat Technologies Au
Publication of NZ509450A publication Critical patent/NZ509450A/en

Links

Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G07F17/3202—Hardware aspects of a gaming system, e.g. components, construction, architecture thereof
    • G07F17/3223—Architectural aspects of a gaming system, e.g. internal configuration, master/slave, wireless communication

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Pinball Game Machines (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)

Abstract

An electronic Input/Output Interface and device abstraction system used in gaming machine includes: a game central processing unit (the game "CPU"); an intelligent input/output controller board (the "IOCB"); an Industry Standard Architecture PC bus ("IBA bus"); and a framed message transport protocol. The IOCB facilitates the communications between the game CPU and virtual device services, which, are peripheral devices associated with the gaming system. These include devices such as displays, buttons, hoppers, coin mechanisms and bill validators. The framed message transport protocol includes: a message header, a body containing a virtual device message, and a packet validation signature. The game CPU communicates to gaming peripherals by sending virtual device messages across the ISA bus to the IOCB. The IOCB then routes the virtual device message to the appropriate virtual device services. The virtual device services are responsible for handling specific hardware, and are made up of virtual device drivers on the game CPU that communicate with virtual devices on the IOCB and use of the IOCB and the high speed interface enables the game CPU to use more of its available functions for controlling gaming functions rather than one operation of its associated peripheral devices.
NZ509450A 1998-07-24 1999-07-23 Input/output interface and device abstraction NZ509450A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9406898P 1998-07-24 1998-07-24
PCT/AU1999/000595 WO2000006268A1 (en) 1998-07-24 1999-07-23 Input/output interface and device abstraction

Publications (1)

Publication Number Publication Date
NZ509450A true NZ509450A (en) 2003-03-28

Family

ID=22242681

Family Applications (1)

Application Number Title Priority Date Filing Date
NZ509450A NZ509450A (en) 1998-07-24 1999-07-23 Input/output interface and device abstraction

Country Status (4)

Country Link
AU (1) AU748434B2 (en)
NZ (1) NZ509450A (en)
WO (1) WO2000006268A1 (en)
ZA (1) ZA200100616B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6607441B1 (en) 1998-04-28 2003-08-19 Acres Gaming Incorporated Method for transferring credit from one gaming machine to another
US7290072B2 (en) * 1999-10-06 2007-10-30 Igt Protocols and standards for USB peripheral communications
US9555322B2 (en) 2001-08-20 2017-01-31 Bally Gaming, Inc. Local game-area network method
US8065394B2 (en) 2001-08-20 2011-11-22 Bally Gaming, Inc. Local game-area network method
US7351151B1 (en) 2001-08-20 2008-04-01 Sierra Design Group Gaming board set and gaming kernel for game cabinets
US7966485B2 (en) * 2004-12-01 2011-06-21 Igt Universal operating system to hardware platform interface for gaming machines

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3788346T2 (en) * 1986-11-04 1994-06-23 Unisys Corp I / O SYSTEM FOR UNLOADING OPERATING SYSTEM FUNCTIONS.
AU695704B2 (en) * 1994-10-12 1998-08-20 Sega Enterprises, Ltd. Improvement in communication between data processing apparatus and peripheral device thereof

Also Published As

Publication number Publication date
AU4890099A (en) 2000-02-21
AU748434B2 (en) 2002-06-06
ZA200100616B (en) 2002-06-26
WO2000006268A1 (en) 2000-02-10

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Legal Events

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PSEA Patent sealed
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