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MX2018014628A - Estructura de memoria caché de varios niveles. - Google Patents

Estructura de memoria caché de varios niveles.

Info

Publication number
MX2018014628A
MX2018014628A MX2018014628A MX2018014628A MX2018014628A MX 2018014628 A MX2018014628 A MX 2018014628A MX 2018014628 A MX2018014628 A MX 2018014628A MX 2018014628 A MX2018014628 A MX 2018014628A MX 2018014628 A MX2018014628 A MX 2018014628A
Authority
MX
Mexico
Prior art keywords
cache
level
cache structure
levels
caches
Prior art date
Application number
MX2018014628A
Other languages
English (en)
Other versions
MX389840B (es
Inventor
Busayarat Sata
Arthur Gay Allen
David Lutz Jonathan
Qi Mei
Original Assignee
Home Box Office Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Home Box Office Inc filed Critical Home Box Office Inc
Publication of MX2018014628A publication Critical patent/MX2018014628A/es
Publication of MX389840B publication Critical patent/MX389840B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/2866—Architectures; Arrangements
    • H04L67/2885—Hierarchically arranged intermediate devices, e.g. for hierarchical caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H04L67/5681—Pre-fetching or pre-delivering data based on network characteristics
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/314—In storage network, e.g. network attached cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

La tecnología descrita se dirige hacia una estructura de memoria caché que accede a un nivel de memorias caché ordenadas, en orden de niveles, para cumplir las solicitudes de datos. La estructura de memoria caché puede implementarse en un servidor de nivel de servicio frontal, y/o en un servidor de nivel de servicio interno, o ambos. La estructura de memoria caché maneja las operaciones de lectura directa y escritura directa, que incluyen el manejo de solicitudes por lotes para múltiples elementos de datos. La estructura de memoria caché también facilita el cambio dinámico de la estructura de niveles, por ejemplo. Para agregar, eliminar, reemplazar y/o reordenar las memorias caché en el nivel, por ejemplo, al declarar nuevamente una estructura de datos como una matriz que identifica la configuración de memoria caché en niveles.
MX2018014628A 2016-05-27 2017-05-26 Estructura de memoria caché de varios niveles MX389840B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/167,321 US10404823B2 (en) 2016-05-27 2016-05-27 Multitier cache framework
PCT/US2017/034746 WO2017205782A1 (en) 2016-05-27 2017-05-26 Multitier cache framework

Publications (2)

Publication Number Publication Date
MX2018014628A true MX2018014628A (es) 2019-07-18
MX389840B MX389840B (es) 2025-03-20

Family

ID=59014841

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2018014628A MX389840B (es) 2016-05-27 2017-05-26 Estructura de memoria caché de varios niveles

Country Status (6)

Country Link
US (2) US10404823B2 (es)
EP (1) EP3465447B1 (es)
CO (1) CO2018014245A2 (es)
MX (1) MX389840B (es)
SG (1) SG11201811666WA (es)
WO (1) WO2017205782A1 (es)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10432531B2 (en) * 2016-06-28 2019-10-01 Paypal, Inc. Tapping network data to perform load balancing
US10536551B2 (en) * 2017-01-06 2020-01-14 Microsoft Technology Licensing, Llc Context and social distance aware fast live people cards
CN109614347B (zh) * 2018-10-22 2023-07-21 中国平安人寿保险股份有限公司 多级缓存数据的处理方法、装置、存储介质及服务器
US11392657B2 (en) 2020-02-13 2022-07-19 Microsoft Technology Licensing, Llc Intelligent selection and presentation of people highlights on a computing device
US11340907B2 (en) 2020-07-06 2022-05-24 Lilac Cloud, Inc. Command-aware hardware architecture
US11206313B1 (en) 2020-09-09 2021-12-21 Oracle International Corporation Surrogate cache for optimized service access with compact user objects and offline database updates
US11616849B2 (en) * 2021-02-15 2023-03-28 Lilac Cloud, Inc. Distributed split edge application architecture
JP7412397B2 (ja) * 2021-09-10 2024-01-12 株式会社日立製作所 ストレージシステム
US12289490B2 (en) 2022-11-17 2025-04-29 Lilac Cloud, Inc. Application cache acceleration using device content cache

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542964B1 (en) 1999-06-02 2003-04-01 Blue Coat Systems Cost-based optimization for content distribution using dynamic protocol selection and query resolution for cache server
US7289964B1 (en) * 1999-08-31 2007-10-30 Accenture Llp System and method for transaction services patterns in a netcentric environment
US6732237B1 (en) * 2000-08-29 2004-05-04 Oracle International Corporation Multi-tier caching system
US9003376B2 (en) * 2002-08-09 2015-04-07 Texas Instruments Incorporated Software breakpoints with tailoring for multiple processor shared memory or multiple thread systems
TWI227409B (en) * 2003-06-05 2005-02-01 Carry Computer Eng Co Ltd Storage device capable of enhancing transmission speed
US20050050455A1 (en) * 2003-08-29 2005-03-03 Yee Sunny K. Method and apparatus for supporting object caching in a web presentation architecture
US7613876B2 (en) * 2006-06-08 2009-11-03 Bitmicro Networks, Inc. Hybrid multi-tiered caching storage system
US8180720B1 (en) 2007-07-19 2012-05-15 Akamai Technologies, Inc. Content delivery network (CDN) cold content handling
US9355109B2 (en) * 2010-06-11 2016-05-31 The Research Foundation For The State University Of New York Multi-tier caching
US20120089700A1 (en) 2010-10-10 2012-04-12 Contendo, Inc. Proxy server configured for hierarchical caching and dynamic site acceleration and custom object and associated method
WO2014025972A2 (en) 2012-08-09 2014-02-13 Limelight Networks, Inc. Inter point of presence split architecture
US8962534B2 (en) * 2012-09-07 2015-02-24 Bosque Systems, Llc Systems and methods of treating water used for hydraulic fracturing
US20150074222A1 (en) 2013-09-12 2015-03-12 Guanfeng Liang Method and apparatus for load balancing and dynamic scaling for low delay two-tier distributed cache storage system
WO2016064039A1 (ko) 2014-10-21 2016-04-28 엘지전자(주) 저 지연을 지원하는 무선 통신 시스템에서 데이터 송수신 방법 및 이를 위한 장치

Also Published As

Publication number Publication date
CO2018014245A2 (es) 2019-01-18
US20190387071A1 (en) 2019-12-19
WO2017205782A1 (en) 2017-11-30
US20170346917A1 (en) 2017-11-30
CA3029298A1 (en) 2017-11-30
EP3465447B1 (en) 2025-07-16
MX389840B (es) 2025-03-20
SG11201811666WA (en) 2019-01-30
US11146654B2 (en) 2021-10-12
US10404823B2 (en) 2019-09-03
EP3465447A1 (en) 2019-04-10

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