An atomic instruction is a full barrier to everything?

Posted Jun 5, 2024 10:46 UTC (Wed) by farnz (subscriber, #17727)
In reply to: An atomic instruction is a full barrier to everything? by epa
Parent article: An instruction-level BPF memory model

There are CPUs that are ultra-strict like that (all x86 CPUs, I believe, meet this requirement); in your example, though, the detail you're missing is that if no other code uses r9 or address 123, there's no way to tell if the swap instruction was executed.

And it's a one-way condition; if the swap instruction was executed, then you know that all instructions before the swap instruction were executed. But if you do not know whether or not the swap instruction was executed, you do not know if the instructions before it are visible or not - and if you neither look at r9, nor inspect address 123, how do you know it executed?

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An atomic instruction is a full barrier to everything?

Posted Jun 5, 2024 10:57 UTC (Wed) by epa (subscriber, #39769) [Link] (1 responses)

Yes I see your point. So a more pedantic way to state the property would be that “if the effect of the atomic instruction is visible then the effects of all instructions before it are visible”.

An atomic instruction is a full barrier to everything?

Posted Jun 5, 2024 11:14 UTC (Wed) by farnz (subscriber, #17727) [Link]

Yes, and that's implicit in virtually all descriptions of memory ordering; what we normally talk about is "happens-before" ordering, where we say that A happens-before B if and only if we can deduce that A must have happened given that we can demonstrate that B has happened.

There's also sometimes the need to talk about whether a happens-before ordering is global (i.e. if thread X sees that A happens-before B, then thread Y must agree that A happens-before B) or local (if thread X sees that A happens-before B, thread Y could still see that B happens-before A, that A happens-before B, or that there's no ordering relationship between A and B). This is, I think what you were reaching towards; an atomic instruction does not always guarantee a global ordering, but on x86, it's defined as doing so (LOCK prefixes are defined this way).