Whither WireGuard?

Posted Mar 26, 2019 8:58 UTC (Tue) by nhippi (subscriber, #34640)
Parent article: Whither WireGuard?

It's fascinating to watch the constant ebb and flow between CPU and accelerators. We find running things on CPU to slow or too power consuming, and implement specialized accelerator HW to deal with. Then we find the specialized HW to limiting and cumbersome to use, and retreat back to doing things on the general purpose CPU. Only to repeat the cycle in future.

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Whither WireGuard?

Posted Mar 26, 2019 10:12 UTC (Tue) by eru (subscriber, #2753) [Link] (1 responses)

The phenomenon has been noticed long ago, it even has an entry in the Jargon file: http://catb.org/jargon/html/W/wheel-of-reincarnation.html

Whither WireGuard?

Posted Mar 26, 2019 10:54 UTC (Tue) by darwish (guest, #102479) [Link]

And in any kind of a complicated “system” (sw/hw/teams):

https://lwn.net/Articles/783496/

Whither WireGuard?

Posted Mar 26, 2019 18:20 UTC (Tue) by HenrikH (subscriber, #31152) [Link] (8 responses)

In the future CPU:s should perhaps add a big chunk of FPGA and just let the kernel implement their own offloading algorithms.

Whither WireGuard?

Posted Mar 26, 2019 19:02 UTC (Tue) by zdzichu (subscriber, #17118) [Link] (6 responses)

By future you mean last year?
https://www.anandtech.com/show/12773/intel-shows-xeon-sca...

Whither WireGuard?

Posted Mar 27, 2019 0:37 UTC (Wed) by dskoll (subscriber, #1630) [Link]

I like the cost column for the processor with the FPGA: "arm, leg"

Whither WireGuard?

Posted Mar 27, 2019 5:50 UTC (Wed) by ofranja (subscriber, #11084) [Link] (4 responses)

By last year you mean 8 years ago?

http://www.newelectronics.co.uk/electronics-news/embedded...

Whither WireGuard?

Posted Mar 27, 2019 6:34 UTC (Wed) by jem (subscriber, #24231) [Link] (3 responses)

Xilinx's solution solves what could be called the opposite problem by adding a CPU to an FPGA. The CPU is used for slow and complex sequential logic supporting the main function of the chip, which is implemented using the programmable logic. The idea is to save silicon area by including a hardwired CPU core instead of a syntehsized one.

Whither WireGuard?

Posted Mar 27, 2019 14:15 UTC (Wed) by dskoll (subscriber, #1630) [Link] (1 responses)

The hard CPU cores in FPGAs are typically ARM cores that don't have stellar performance (this is true even for Alterra/Intel). Putting FPGA fabric in a high-performance CPU approaches the problem from the other direction and is quite interesting.

I suspect, though, that any cool designs implemented in an FPGA will eventually migrate either to a hard core or into the CPU for performance reasons. I think the FPGA fabric is mostly interesting as a prototyping solution.

Whither WireGuard?

Posted Mar 28, 2019 2:24 UTC (Thu) by raven667 (subscriber, #5198) [Link]

I think that is complementary with the original idea, a CPU with FPGA could deploy arbitrary new hardware features, anything that becomes ubiquitous can be reimplemented in fixed logic in later CPUs, freeing up FPGA for new uses. You get to have feedback about which hardware features are actually practical to developers before having to work them into the fixed design.

I don't know if that makes sense from the perspective of the chip real estate budget, would that area be better used for cache or something more mundane, would FPGA change the manufacturing cost? It's an interesting idea anyway

Whither WireGuard?

Posted Mar 27, 2019 19:32 UTC (Wed) by ofranja (subscriber, #11084) [Link]

For the embedded market, it's usually the trifecta time-to-market/cost/power.

Synthesizing an ARM processor this size would be really wasteful on an FPGA. I don't see anyone doing that in a product without a very strong reason (and a very good margin as well, to buffer the excess cost).

Whither WireGuard?

Posted Mar 28, 2019 15:13 UTC (Thu) by ejr (subscriber, #51652) [Link]

Oh, and don't forget the programmable NICs with CPU + FPGA + RAM combos embedded. What goes around...