Overview
- Describes SAT-based model checking approaches and gives engineering details on what makes model checking practical
- Techniques covered can be synergistically combined into a scalabe solution
- Focuses on engineering design and not mathematics
- Includes supplementary material: sn.pub/extras
Part of the book series: Integrated Circuits and Systems (ICIR)
Access this book
Tax calculation will be finalised at checkout
Other ways to access
About this book
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors.
SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol.
The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.
Similar content being viewed by others
Table of contents (13 chapters)
-
Front Matter
-
Design Verification Challenges
-
Basic Infrastructure
-
Front Matter
-
-
Falsification
-
Front Matter
-
-
Proof Methods
-
Front Matter
-
-
Abstraction/Refinement
-
Front Matter
-
-
Verification Procedure
-
Front Matter
-
-
Back Matter
Authors and Affiliations
Accessibility Information
Accessibility information for this book is coming soon. We're working to make it available as quickly as possible. Thank you for your patience.
Bibliographic Information
Book Title: SAT-Based Scalable Formal Verification Solutions
Authors: Malay K. Ganai, Aarti Gupta
Series Title: Integrated Circuits and Systems
DOI: https://doi.org/10.1007/978-0-387-69167-1
Publisher: Springer New York, NY
eBook Packages: Computer Science, Computer Science (R0)
Copyright Information: Springer-Verlag US 2007
Hardcover ISBN: 978-0-387-69166-4Published: 22 May 2007
Softcover ISBN: 978-1-4419-4341-5Published: 19 November 2010
eBook ISBN: 978-0-387-69167-1Published: 26 May 2007
Series ISSN: 1558-9412
Series E-ISSN: 1558-9420
Edition Number: 1
Number of Pages: XXX, 330
Number of Illustrations: 118 b/w illustrations
Topics: Computer-Aided Engineering (CAD, CAE) and Design, Circuits and Systems, Electrical Engineering