From c7f2fe92deea55e609c23ccdd0100a35fcbf3981 Mon Sep 17 00:00:00 2001 From: Neelay Sant Date: Mon, 20 Jan 2025 11:31:27 +0000 Subject: [PATCH] RISC-V: Fix width inlined with CNop. Change width check to using inlined width. --- .../lib/src/machine_state/block_cache.rs | 12 +++++-- .../lib/src/machine_state/instruction.rs | 32 ++++--------------- 2 files changed, 16 insertions(+), 28 deletions(-) diff --git a/src/riscv/lib/src/machine_state/block_cache.rs b/src/riscv/lib/src/machine_state/block_cache.rs index 20bf5d0ab147..abb2c5cb5401 100644 --- a/src/riscv/lib/src/machine_state/block_cache.rs +++ b/src/riscv/lib/src/machine_state/block_cache.rs @@ -524,7 +524,11 @@ impl, ML: MainMemoryLayout, M: Mana where M: ManagerReadWrite, { - debug_assert_eq!(instr.width(), InstrWidth::Compressed); + debug_assert_eq!( + instr.width(), + InstrWidth::Compressed, + "expected compressed instruction, found: {instr:?}" + ); let next_addr = self.next_instr_addr.read(); @@ -542,7 +546,11 @@ impl, ML: MainMemoryLayout, M: Mana where M: ManagerReadWrite, { - debug_assert_eq!(instr.width(), InstrWidth::Uncompressed); + debug_assert_eq!( + instr.width(), + InstrWidth::Uncompressed, + "expected uncompressed instruction, found: {instr:?}" + ); // ensure uncompressed does not cross page boundaries const END_OF_PAGE: Address = PAGE_SIZE - 2; diff --git a/src/riscv/lib/src/machine_state/instruction.rs b/src/riscv/lib/src/machine_state/instruction.rs index 3d809e65ef18..4b54eaaf83ef 100644 --- a/src/riscv/lib/src/machine_state/instruction.rs +++ b/src/riscv/lib/src/machine_state/instruction.rs @@ -124,30 +124,7 @@ impl Debug for Instruction { impl Instruction { /// Returns the width of the instruction: either compressed or uncompressed. pub const fn width(&self) -> InstrWidth { - use OpCode::*; - match self.opcode { - Add | Sub | Xor | Or | And | Sll | Srl | Sra | Slt | Sltu | Addw | Subw | Sllw - | Srlw | Sraw | Addi | Addiw | Xori | Ori | Andi | Slli | Srli | Srai | Slliw - | Srliw | Sraiw | Slti | Sltiu | Lb | Lh | Lw | Lbu | Lhu | Lwu | Ld | Sb | Sh | Sw - | Sd | Beq | Bne | Blt | Bge | Bltu | Bgeu | Lui | Auipc | Jal | Jalr | Lrw | Scw - | Amoswapw | Amoaddw | Amoxorw | Amoandw | Amoorw | Amominw | Amomaxw | Amominuw - | Amomaxuw | Lrd | Scd | Amoswapd | Amoaddd | Amoxord | Amoandd | Amoord | Amomind - | Amomaxd | Amominud | Amomaxud | Rem | Remu | Remw | Remuw | Div | Divu | Divw - | Divuw | Mul | Mulh | Mulhsu | Mulhu | Mulw | FclassS | Feqs | Fles | Flts | Fadds - | Fsubs | Fmuls | Fdivs | Fsqrts | Fmins | Fmaxs | Fmadds | Fmsubs | Fnmsubs - | Fnmadds | Flw | Fsw | Fcvtsw | Fcvtswu | Fcvtsl | Fcvtslu | Fcvtws | Fcvtwus - | Fcvtls | Fcvtlus | Fsgnjs | Fsgnjns | Fsgnjxs | FmvXW | FmvWX | FclassD | Feqd - | Fled | Fltd | Faddd | Fsubd | Fmuld | Fdivd | Fsqrtd | Fmind | Fmaxd | Fmaddd - | Fmsubd | Fnmsubd | Fnmaddd | Fld | Fsd | Fcvtdw | Fcvtdwu | Fcvtdl | Fcvtdlu - | Fcvtds | Fcvtsd | Fcvtwd | Fcvtwud | Fcvtld | Fcvtlud | Fsgnjd | Fsgnjnd - | Fsgnjxd | FmvXD | FmvDX | Csrrw | Csrrs | Csrrc | Csrrwi | Csrrsi | Csrrci - | Unknown => InstrWidth::Uncompressed, - - CLw | CLwsp | CSw | CSwsp | CJ | CJr | CJalr | CBeqz | CBnez | CLi | CLui | CAddi - | CAddi16sp | CAddi4spn | CSlli | CSrli | CSrai | CAndi | CMv | CAdd | CAnd | COr - | CXor | CSub | CAddw | CSubw | CNop | CLd | CLdsp | CSd | CSdsp | CAddiw | CFld - | CFldsp | CFsd | CFsdsp | UnknownCompressed => InstrWidth::Compressed, - } + self.args.width } /// Returns a reference to the arguments of an instruction. @@ -1327,7 +1304,7 @@ impl Args { fn run_cnop(&self, icb: &mut I) -> ::IResult { c::run_cnop(icb); - icb.ok(Next(InstrWidth::Compressed)) + icb.ok(Next(self.width)) } // RV64C compressed instructions @@ -2085,7 +2062,10 @@ impl From<&InstrCacheable> for Instruction { }, InstrCacheable::CNop => Instruction { opcode: OpCode::CNop, - args: Args::DEFAULT, + args: Args { + width: InstrWidth::Compressed, + ..Args::DEFAULT + }, }, // RV64C compressed instructions -- GitLab