diff --git a/src/riscv/lib/src/machine_state/bus.rs b/src/riscv/lib/src/machine_state/bus.rs
index ac4bd3a6ba661ff5504eb8f5d290e980666a38a1..ee5da134318ae27dab8d57bf76f706a6a773ec3e 100644
--- a/src/riscv/lib/src/machine_state/bus.rs
+++ b/src/riscv/lib/src/machine_state/bus.rs
@@ -90,7 +90,7 @@ pub struct Bus<ML: main_memory::MainMemoryLayout, M: backend::ManagerBase> {
     memory: main_memory::MainMemory<ML, M>,
 }
 
-impl<ML: main_memory::MainMemoryLayout, M: backend::Manager> Bus<ML, M> {
+impl<ML: main_memory::MainMemoryLayout, M: backend::ManagerBase> Bus<ML, M> {
     /// Bind the Bus state to the allocated space.
     pub fn bind(space: backend::AllocatedOf<BusLayout<ML>, M>) -> Self {
         Self {
@@ -100,7 +100,10 @@ impl<ML: main_memory::MainMemoryLayout, M: backend::Manager> Bus<ML, M> {
     }
 
     /// Reset the bus state.
-    pub fn reset(&mut self) {
+    pub fn reset(&mut self)
+    where
+        M: backend::ManagerWrite,
+    {
         self.devices.reset();
         self.memory.reset();
     }