From 71089ffd00c266eaa684e97bb156f3af2308ce73 Mon Sep 17 00:00:00 2001
From: Emma Turner <emma.turner@trili.tech>
Date: Wed, 27 Mar 2024 17:01:51 +0000
Subject: [PATCH] RISC-V: ensure f32s are nan-boxed

---
 src/risc_v/interpreter/src/interpreter/rv64f.rs | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/risc_v/interpreter/src/interpreter/rv64f.rs b/src/risc_v/interpreter/src/interpreter/rv64f.rs
index ae1bf6312bf2..35ba418d055d 100644
--- a/src/risc_v/interpreter/src/interpreter/rv64f.rs
+++ b/src/risc_v/interpreter/src/interpreter/rv64f.rs
@@ -6,6 +6,7 @@
 //!
 //! Chapter 11 - "F" Standard Extension for Single-Precision Floating-Point
 
+use super::float::FloatExt;
 use crate::{
     machine_state::{
         bus::main_memory::MainMemoryLayout,
@@ -29,7 +30,14 @@ impl From<Single> for FValue {
 impl Into<Single> for FValue {
     fn into(self) -> Single {
         let val: u64 = self.into();
-        Single::from_bits(val as u32 as u128)
+
+        // Check value correctly NaN boxed:
+        // all upper bits must be set to 1
+        if val >> 32 != 0xffffffff {
+            Single::canonical_nan()
+        } else {
+            Single::from_bits(val as u32 as u128)
+        }
     }
 }
 
-- 
GitLab