From e5a6cb690188e726285e11db510bf178a0da4636 Mon Sep 17 00:00:00 2001 From: vibe-coder Date: Sun, 8 Jun 2025 21:30:14 +0200 Subject: [PATCH] cartridge logging refactoring --- include/core/cartridge.hpp | 12 +++++------- src/cartridge_impls/nombc.cpp | 23 ++++++++++++----------- src/core/cartridge.cpp | 34 ++++++++++++++++++++-------------- src/raylib/main.cpp | 18 +++++++++--------- 4 files changed, 46 insertions(+), 41 deletions(-) diff --git a/include/core/cartridge.hpp b/include/core/cartridge.hpp index 211d781..801c7c7 100644 --- a/include/core/cartridge.hpp +++ b/include/core/cartridge.hpp @@ -33,6 +33,8 @@ protected: unsigned romBankCount = 0; unsigned ramBankCount = 0; + constexpr static uint8_t invalidReadValue = 0xFF; // Value returned on invalid read + public: static std::unique_ptr create( CartridgeType type, std::vector&& rom ); @@ -74,14 +76,12 @@ enum class CoreCartridge::CartridgeType : uint8_t { MBC5RuR, // MBC5 with Rumble and RAM MBC5RuRB, // MBC5 with Rumble, RAM and Battery - // clang-format off MBC6 = 0x20, MBC7SensorRuRB = 0x22, // MBC7 with Sensor, Rumble, RAM and Battery PocketCamera = 0xFC, BandaiTama5 = 0xFD, HuC3 = 0xFE, - HuC1RB = 0xFF // HuC1 with RAM and Battery - // clang-format on + HuC1RB = 0xFF, // HuC1 with RAM and Battery }; // Note: @@ -99,21 +99,19 @@ enum class CoreCartridge::RomSize : uint8_t { _8MiB, _1_1MiB = 0x52, // 1.1 MiB _1_2MiB, // 1.2 MiB - _1_5MiB // 1.5 MiB + _1_5MiB, // 1.5 MiB }; // Note: // RAM consists of 8KiB banks // 2 KiB chip was never used in a cartridges enum class CoreCartridge::RamSize : uint8_t { - // clang-format off _0KiB = 0x00, _2KiB, _8KiB, _32KiB, _128KiB, - _64KiB - // clang-format on + _64KiB, }; namespace addr { diff --git a/src/cartridge_impls/nombc.cpp b/src/cartridge_impls/nombc.cpp index 302850b..cbedb65 100644 --- a/src/cartridge_impls/nombc.cpp +++ b/src/cartridge_impls/nombc.cpp @@ -6,35 +6,36 @@ NoMBCCartridge::NoMBCCartridge( std::vector&& rom_ ) : CoreCartridge( std::move( rom_ ) ) {}; uint8_t NoMBCCartridge::read( const uint16_t address ) { - logDebug( std::format( "Trying to read at address 0x{:04X}", address ) ); + logDebug( std::format( "Trying to read at address {}", toHex( address ) ) ); if( romStartAddress <= address && address < ( romStartAddress + romBankSize * romBankCount ) ) { unsigned bankIndex = address / romBankSize; uint16_t bankOffset = address % romBankSize; auto returnValue = romBanks[bankIndex][bankOffset]; - logInfo( std::format( "Read value 0x{:02X} from ROM bank {} at offset 0x{:04X}", returnValue, - bankIndex, bankOffset ) ); + logInfo( std::format( "Read value {} from ROM bank {} at offset {}", toHex( returnValue ), bankIndex, + toHex( bankOffset ) ) ); return returnValue; } if( ramBankCount <= 0 ) { - logWarning( 0, std::format( "No RAM banks available. Returning 0x{:02X}", 0xFF ) ); - return 0xFF; + logWarning( 0, std::format( "No RAM banks available. Returning {}", toHex( invalidReadValue ) ) ); + return invalidReadValue; } if( ramStartAddress <= address && address < ( ramStartAddress + ramBankSize ) ) { auto returnValue = ramBanks[0][address - ramStartAddress]; - logInfo( std::format( "Read value 0x{:02X} from RAM bank {} at address 0x{:04X}", 0, returnValue, - address ) ); + logInfo( std::format( "Read value {} from RAM bank {} at address {}", toHex( returnValue ), 0, + toHex( address ) ) ); return returnValue; } - return 0xFF; + logWarning( 0, std::format( "Address out of supported range. Returning {}", toHex( invalidReadValue ) ) ); + return invalidReadValue; } void NoMBCCartridge::write( const uint16_t address, const uint8_t value ) { - logDebug( std::format( "Trying to write value 0x{:02X} to address 0x{:04X}", value, address ) ); + logDebug( std::format( "Trying to write value {} to address {}", toHex( value ), toHex( address ) ) ); if( ramBankCount <= 0 ) { logWarning( 0, "No RAM banks available. Write operation ignored." ); @@ -42,11 +43,11 @@ void NoMBCCartridge::write( const uint16_t address, const uint8_t value ) { } if( address < ramStartAddress || address >= ( ramStartAddress + ramBankSize ) ) { - logWarning( 0, std::format( "Invalid address 0x{:04X}", address ) ); + logWarning( 0, std::format( "Invalid address {}", toHex( address ) ) ); return; } // Only first RAM bank is supported in NoMBC ramBanks[0][address - ramStartAddress] = value; - logDebug( std::format( "Wrote value 0x{:02X} to address 0x{:04X}", value, address ) ); + logDebug( std::format( "Wrote value {} to address {}", toHex( value ), toHex( address ) ) ); } diff --git a/src/core/cartridge.cpp b/src/core/cartridge.cpp index 81b99df..c79027e 100644 --- a/src/core/cartridge.cpp +++ b/src/core/cartridge.cpp @@ -45,8 +45,8 @@ bool CoreCartridge::isValidRomSize( const RomSize size ) { default: break; } - logError( 0, std::format( "ROM size unknown. Byte: 0x{:02X}", - static_cast>( size ) ) ); + logError( 0, std::format( "ROM size unknown. Byte: {}", + toHex( static_cast>( size ) ) ) ); return false; } @@ -65,10 +65,11 @@ void CoreCartridge::initRom( const RomSize size ) { for( unsigned i = 0; i < romBankCount; ++i ) { auto offset = i * romBankSize; romBanks.emplace_back( rom.data() + offset, romBankSize ); - logDebug( std::format( "Initialized ROM bank {} at offset 0x{:04X} of size 0x{:04X}", i, offset, - romBankSize ) ); + logDebug( std::format( "Initialized ROM bank {} at offset {} of size {}", i, + toHex( offset ), toHex( romBankSize ) ) ); } - logInfo( std::format( "Initialized {} ROM banks of size 0x{:04X} bytes", romBanks.size(), romBankSize ) ); + logInfo( std::format( "Initialized {} ROM banks of size {} bytes", romBanks.size(), + toHex( romBankSize ) ) ); } bool CoreCartridge::isValidRamSize( const RamSize size ) { @@ -87,8 +88,8 @@ bool CoreCartridge::isValidRamSize( const RamSize size ) { default: break; } - logError( 0, std::format( "RAM size unknown. Byte: 0x{:02X}", - static_cast>( size ) ) ); + logError( 0, std::format( "RAM size unknown. Byte: {}", + toHex( static_cast>( size ) ) ) ); return false; } @@ -122,16 +123,21 @@ void CoreCartridge::initRam( const CoreCartridge::RamSize size ) { } ramBanks = std::vector>( ramBankCount, std::vector( ramBankSize, 0 ) ); - logInfo( std::format( "Initialized {} RAM banks of size 0x{:04X} bytes", ramBanks.size(), ramBankSize ) ); + logInfo( std::format( "Initialized {} RAM banks of size {} bytes", ramBanks.size(), + toHex( ramBankSize ) ) ); } CoreCartridge::CoreCartridge( std::vector&& rom_ ) : rom( std::move( rom_ ) ) { logDebug( "CoreCartridge constructor" ); - logDebug( std::format( "Read ROM size byte: 0x{:02X} bytes", rom[0x148] ) ); - logDebug( std::format( "Read RAM size byte: 0x{:02X} bytes", rom[0x149] ) ); - initRom( static_cast( rom[0x148] ) ); - initRam( static_cast( rom[0x149] ) ); + const auto romSizeByte = rom[addr::romSize]; + logDebug( std::format( "Read ROM size byte: {} bytes", toHex( romSizeByte ) ) ); + initRom( static_cast( romSizeByte ) ); + + + const auto ramSizeByte = rom[addr::ramSize]; + logDebug( std::format( "Read RAM size byte: {} bytes", toHex( ramSizeByte ) ) ); + initRam( static_cast( ramSizeByte ) ); }; std::unique_ptr CoreCartridge::create( CartridgeType type, std::vector&& rom ) { @@ -149,7 +155,7 @@ std::unique_ptr CoreCartridge::create( CartridgeType type, std::v default: break; } - logError( 0, std::format( "Unknown cartridge type: 0x{:02X}", - static_cast>( type ) ) ); + logError( 0, std::format( "Unknown cartridge type: {}", + toHex( static_cast>( type ) ) ) ); return nullptr; } diff --git a/src/raylib/main.cpp b/src/raylib/main.cpp index 9f029e6..c5a36e2 100644 --- a/src/raylib/main.cpp +++ b/src/raylib/main.cpp @@ -1,3 +1,4 @@ +#include "core/cartridge.hpp" #include "core/emulator.hpp" #include "core/logging.hpp" #include "raylib/raylib_parts.hpp" @@ -35,19 +36,18 @@ int main() { romFile.close(); - CoreCartridge::CartridgeType type = static_cast( romData[0x147] ); + CoreCartridge::CartridgeType type = static_cast( romData[addr::romSize] ); std::unique_ptr cartridge { CoreCartridge::create( type, std::move( romData ) ) }; + logDebug( std::format( "Read cartridge type byte: {}", toHex( cartridge->read( addr::cartridgeType ) ) ) ); + logDebug( std::format( "Read ROM size byte: {}", toHex( cartridge->read( addr::romSize ) ) ) ); + logDebug( std::format( "Read RAM size byte: {}", toHex( cartridge->read( addr::ramSize ) ) ) ); - logDebug( std::format( "Read cartridge type byte: 0x{:02X}", cartridge->read( addr::cartridgeType ) ) ); - logDebug( std::format( "Read ROM size byte: 0x{:02X}", cartridge->read( addr::romSize ) ) ); - logDebug( std::format( "Read RAM size byte: 0x{:02X}", cartridge->read( addr::ramSize ) ) ); + logDebug( std::format( "Try to read from ROM bank 1. Read from address {}: {}", + toHex( uint16_t { 0x4000 } ), toHex( cartridge->read( 0x4000 ) ) ) ); - logDebug( std::format( "Try to read from ROM bank 1. Read from address 0x{:04X}: 0x{:02X}", 0x4000, - cartridge->read( 0x4000 ) ) ); - - logDebug( std::format( "Try to read from RAM (which does not exist). Read from address 0x{:04X}: 0x{:02X}", - 0xA000, cartridge->read( 0xA000 ) ) ); + logDebug( std::format( "Try to read from RAM (which does not exist). Read from address {}: {}", + toHex( uint16_t { 0xA000 } ), toHex( cartridge->read( 0xA000 ) ) ) ); const int scaleFactor = 7; const int screenWidth = CorePpu::displayWidth * scaleFactor; -- GitLab