Meta 16bit instructions for Z80

Z80 operates mostly in 8bit units in the provided instruction set. A few exceptions are found in instructions such as ADD HL,rr, where Z80 performs the full 16bit work as part of the instruction.

Because of the 8bit architecture of Z80, 16bit register operations done on 16bit register pairs mostly require two instructions, such as ld bc,hl being implemented by ld b,h and ld c,l (stack operations are embedded 16bit but works in steps of 8bit through the databus).

Z380 is a 16bit architecture where most the core load and arithmetic/logic operations (ALU) have dedicated instruction opcodes for the meta instructions to be implemented for Z80.

Since Mpm supports Z80, Z180, Z80N (Spectrum Next) and Z380, the purpose of the meta instructions is to be syntax-compatible with Z380 as much as possible.

Meta Instruction	Z80 instruction	Z80 opcodes	Z380 instruction	Z380 Opcodes
ex bc,de	push bc : ld b,d : ld c,e : pop de	C5 42 4B D1	ex bc,de	ED 05
ex bc,hl	push bc : ld b,h : ld c,l : pop hl	C5 44 4D E1	ex bc,hl	ED 0D
ex bc,ix	push bc : ex (sp),ix : pop bc	C5 DD E3 C1	ex bc,ix	ED 03
ex bc,iy	push bc : ex (sp),iy : pop bc	C5 FD E3 C1	ex bc,iy	ED 0B
ex de,ix	push de : ex (sp),ix : pop de	D5 DD E3 D1	ex de,ix	ED 13
ex de,iy	push de : ex (sp),iy : pop de	D5 FD E3 D1	ex de,iy	ED 1B
ex hl,ix	push hl : ex (sp),ix : pop hl	E5 DD E3 E1	ex hl,ix	ED 33
ex hl,iy	push hl : ex (sp),iy : pop hl	E5 FD E3 E1	ex hl,iy	ED 3B
ex ix,iy	push ix : ex (sp),iy : pop ix	DD E5 FD E3 DD E1	ex ix,iy	ED 2B
ld bc,bc	ld b,b : ld c,c	40 49	ld[w] bc,bc	ED 02
ld bc,bc	ld b,b : ld c,c	40 49	ld[w] bc,bc	ED 02
ld bc,de	ld b,d : ld c,e	42 4B	ld[w] bc,de	DD 02
ld bc,hl	ld b,h : ld c,l	44 4D	ld[w] bc,hl	FD 02
ld bc,ix	ld b,ixh : ld c,ixl	DD 44 DD 4D	ld[w] bc,ix	DD 0B
ld bc,iy	ld b,iyh : ld c,iyl	FD 44 FD 4D	ld[w] bc,iy	FD 0B
ld bc,(hl)	ld c,(hl) : inc hl : ld b,(hl) : dec hl	4E 23 46 30	ld[w] bc,(hl)	DD 0F
ld bc,(ix+n)	ld c,(ix+n) : ld b,(ix+n+1)	DD 4E 00 DD 46 01	ld[w] bc,(ix+n)	DD CB 00 03
ld bc,(iy+n)	ld c,(iy+n) : ld b,(iy+n+1)	FD 4E 00 FD 46 01	ld[w] bc,(iy+n)	FD CB 00 03
ld de,bc	ld d,b : ld e,c	50 59	ld[w] de,bc	ED 12
ld de,de	ld d,d : ld e,e	52 5B	ld[w] de,de	DD 12
ld de,hl	ld d,h : ld e,l	54 5D	ld[w] de,hl	FD 12
ld de,ix	ld d,ixh : ld e,ixl	DD 54 DD 5D	ld[w] de,ix	DD 1B
ld de,iy	ld d,iyh : ld e,iyl	FD 54 FD 5D	ld[w] de,iy	DD 1B
ld de,(hl)	ld e,(hl) : inc hl : ld d,(hl) : dec hl	5E 23 56 30	ld[w] de,(hl)	DD 1F
ld de,(ix+n)	ld e,(ix+n) : ld d,(ix+n+1)	DD 5E 00 DD 56 01	ld[w] de,(ix+n)	DD CB 00 13
ld de,(iy+n)	ld e,(iy+n) : ld d,(iy+n+1)	FD 5E 00 FD 56 01	ld[w] de,(iy+n)	FD CB 00 13
ld hl,bc	ld h,b : ld l,c	60 69	ld[w] hl,bc	ED 32
ld hl,de	ld h,d : ld l,e	62 6B	ld[w] hl,de	DD 32
ld hl,hl	ld h,h : ld l,l	64 6D	ld[w] hl,hl	FD 32
ld hl,ix	push ix : pop hl	DD E5 E1	ld[w] hl,ix	DD 3B
ld hl,iy	push iy : pop hl	FD E5 E1	ld[w] hl,iy	FD 3B
ld hl,(ix+n)	ld l,(ix+n) : ld h,(ix+n+1)	DD 6E 00 DD 66 01	ld[w] hl,(ix+n)	DD CB 00 33
ld hl,(iy+n)	ld l,(iy+n) : ld h,(iy+n+1)	FD 6E 00 FD 66 01	ld[w] hl,(iy+n)	FD CB 00 33
ld ix,bc	ld ixh,b : ld ixl,c	DD 60 DD 69	ld[w] ix,bc	DD 07
ld ix,de	ld ixh,d : ld ixl,e	DD 62 DD 6B	ld[w] ix,de	DD 17
ld ix,hl	push hl : pop ix	E5 DD E1	ld[w] ix,hl	DD 37
ld ix,ix	ld ixh,ixh : ld ixl,ixl	DD 64 DD 6D	Not implemented	Using ld ixh,ixh : ld ixl,ixl would loose upper 16bit access in long word mode
ld ix,iy	push iy : pop ix	FD E5 DD E1	ld[w] ix,iy	DD 27
ld iy,bc	ld iyh,b : ld iyl,c	FD 60 FD 69	ld[w] iy,bc	FD 07
ld iy,de	ld iyh,d : ld iyl,e	FD 62 FD 6B	ld[w] iy,de	FD 17
ld iy,hl	push hl : pop iy	E5 FD E1	ld[w] iy,hl	FD 37
ld iy,ix	push ix : pop iy	DD E5 FD E1	ld[w] iy,ix	FD 27
ld iy,iy	ld iyh,iyh : ld iyl,iyl	FD 64 FD 6D	Not implemented	Using ld iyh,iyh : ld iyl,iyl would loose upper 16bit access in long word mode
ld (hl),bc	ld (hl),c : inc hl : ld (hl),b : dec hl	71 23 70 30	ld[w] (hl),bc	FD 0F
ld (hl),de	ld (hl),e : inc hl : ld (hl),d : dec hl	73 23 72 30	ld[w] (hl),de	FD 1F
ld (ix+n),bc	ld (ix+n),c : ld (ix+n+1),b	DD 71 00 DD 70 01	ld[w] (ix+n),bc	DD CB 00 0B
ld (ix+n),de	ld (ix+n),e : ld (ix+n+1),d	DD 73 00 DD 72 01	ld[w] (ix+n),de	DD CB 00 1B
ld (ix+n),hl	ld (ix+n),l : ld (ix+n+1),h	DD 75 00 DD 74 01	ld[w] (ix+n),hl	DD CB 00 3B
ld (iy+n),bc	ld (iy+n),c : ld (iy+n+1),b	FD 71 00 FD 70 01	ld[w] (iy+n),bc	FD CB 00 0B
ld (iy+n),de	ld (iy+n),e : ld (iy+n+1),d	FD 73 00 FD 72 01	ld[w] (iy+n),de	FD CB 00 1B
ld (iy+n),hl	ld (iy+n),l : ld (iy+n+1),h	FD 75 00 FD 74 01	ld[w] (iy+n),hl	FD CB 00 3B
rl[w] bc	rl c : rl b	CB 11 CB 10	rlw bc	ED CB 10
rl[w] de	rl e : rl d	CB 13 CB 12	rlw de	ED CB 11
rl[w] hl	rl l : rl h	CB 15 CB 14	rlw hl	ED CB 13
rlw (hl)	rl (hl) : inc hl : rl (hl) : dec hl	CB 16 23 CB 16 2B	rlw (hl)	ED CB 12
rr[w] bc	rr b : rr c	CB 18 CB 19	rrw bc	ED CB 18
rr[w] de	rr d : rr e	CB 1A CB 1B	rrw de	ED CB 19
rr[w] hl	rr h : rr l	CB 1C CB 1D	rrw hl	ED CB 1B
rrw (hl)	inc hl : rr (hl) : dec hl : rr (hl)	23 CB 1E 2B CB 1E	rrw (hl)	ED CB 1A
sla[w] bc	sla c : rl b	CB 21 CB 10	slaw bc	ED CB 20
sla[w] de	sla e : rl d	CB 23 CB 12	slaw de	ED CB 21
sla[w] hl	add hl,hl	29	slaw hl	ED CB 23
slaw (hl)	sla (hl) : inc hl : rl (hl) : dec hl	CB 26 23 CB 16 2B	slaw (hl)	ED CB 23
sll	no meta instructions	.	SLL is not implemented	(it's undocumented on Z80)
sra[w] bc	sra b : rr c	CB 28 CB 19	sraw bc	ED CB 28
sra[]w de	sra d : rr e	CB 2A CB 1B	sraw de	ED CB 29
sra[w] hl	sra h : rr l	CB 2C CB 1D	sraw hl	ED CB 2B
sraw (hl)	inc hl : sra (hl) : dec hl : rr (hl)	23 CB 2E 2B CB 1E	sraw (hl)	ED CB 2A
srl[w] bc	srl b : rr c	CB 38 CB 19	srlw bc	ED CB 38
srl[w] de	srl d : rr e	CB 3A CB 1B	srlw de	ED CB 39
srl[w] hl	srl h : rr l	CB 3C CB 1D	srlw hl	ED CB 3B
srlw (hl)	inc hl : srl (hl) : dec hl : rr (hl)	23 CB 3E 2B CB 1E	srlw (hl)	ED CB 3A
sub[w] hl,bc	or a : sbc hl,bc	B7 ED 42	subw hl,bc	ED 94
sub[w] hl,de	or a : sbc hl,de	B7 ED 52	subw hl,de	ED 95
sub[w] hl,hl	or a : sbc hl,hl	B7 ED 62	subw hl,hl	ED 97
sub[w] hl,sp	or a : sbc hl,sp	B7 ED 72	subw [hl,]sp (meta)	B7 ED 72